HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 649

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
15.4
• In master mode, if an instruction to generate a start condition is immediately followed by an
• Either of the following two conditions will start the next transfer. Pay attention to these
• Table 15-6 shows the timing of SCL and SDA output in synchronization with the internal
Table 15-6 I
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
REJ09B0103-0800 Rev. 8.00
May 28, 2010
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
therefore depends on the system clock cycle t
section 24, Electrical Characteristics. Note that the I
will not be met with a system clock frequency of less than 5 MHz.
ICDRT to ICDRS)
ICDRS to ICDRR)
Usage Notes
2
C Bus Timing (SCL and SDA Output)
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
cyc
, as shown in tables 24-19, 24-31, 24-43 in
Output Timing
1 t
28 t
0.5 t
0.5 t
0.5 t
0.5 t
1 t
0.5 t
1 t
3 t
2
C bus interface AC timing specifications
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
(Only for the H8S/2638, H8S/2639, and H8S/2630)
to 256 t
– 3 t
– 3 t
– 1 t
– 1 t
+ 2 t
cyc
cyc
cyc
cyc
cyc
cyc
Section 15 I
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
C Bus Interface [Option]
Page 599 of 1458
Notes
Figure 24-28
(reference)