HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 712

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 Controller Area Network (HCAN)
Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt
source settings and data settings must be made. Interrupt source settings are made in the mailbox
interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are
made by writing the necessary data from the arbitration field, control field, and data field,
described below, in the corresponding message control (MCx[1] to MCx[8]) and message data
(MDx[1] to MDx[8]).
• CPU interrupt source setting
• Arbitration field setting
• Control field setting
• Data field setting
The number of bytes in the data actually transmitted depends on the data length code (DLC) in the
control field. If a value exceeding the value set in DLC is set in the data field, only the number of
bytes set in DLC will actually be transmitted.
Message Transmission and Interrupts:
• Message transmission wait
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Transmission acknowledge and transmission abort acknowledge interrupts can be masked for
individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)
interrupts can be masked in the interrupt mask register (IMR).
In the arbitration field, the 11-bit identifier (STD_ID0 to STD_ID10) and RTR bit (standard
format) or 29-bit identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) and IDE, RTR
bit (extended format) are set. The registers to be set are MCx[5] to MCx[8].
In the control field, the byte length of the data to be transmitted is set in DLC0 to DLC3. The
register to be set is MCx[1].
In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The
registers to be set are MDx[1] to MDx[8].
If message transmission is to be performed after completion of the message control (MCx[1] to
MCx[8]) and message data (MDx[1] to MDx[8]).settings, transmission is started by setting the
corresponding mailbox transmit wait bit (TXPR1 to TXPR15) to 1 in the transmit wait register
(TXPR). The following two transmission methods can be used:
a. Transmission order determined by message identifier priority
b. Transmission order determined by mailbox number priority
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010