HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 718

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 16 Controller Area Network (HCAN)
Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt
source settings and receive message specifications must be made. Interrupt source settings are
made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a
message, the identifier must be set in advance in the message control (MCx[1] to MCx[8]) for the
receiving mailbox. When a message is received, all the bits in the receive message identifier are
compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox
0 (MB0) has a local acceptance filter mask (LAFM) that allows Don’t care settings to be made.
• CPU interrupt source settings
• Arbitration field setting
• Local acceptance filter mask (LAFM) setting
Page 668 of 1458
When transmitting, transmission acknowledge and transmission abort acknowledge interrupts
can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR).
When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt
register (IRR) interrupts can be masked in the interrupt mask register (IMR).
In the arbitration field, the identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) of the
message to be received is set. If all the bits in the set identifier do not match, the message is not
stored in a mailbox.
Example: Mailbox 1
The local acceptance filter mask is provided for mailbox 0 (MB0) only, enabling a Don’t care
specification to be made for all bits in the received identifier. This allows various kinds of
messages to be received.
Example: Mailbox 0
Only one kind of message identifier can be received by MB1
Identifier 1:
LAFM
A total of four kinds of message identifiers can be received by MB0
Identifier 1:
Identifier 2:
Identifier 3:
Identifier 4:
010_1010_1010 (standard identifier)
010_1010_1010
010_1010_1010 (standard identifier)
000_0000_0011 (0: Care, 1: Don’t care)
010_1010_1000
010_1010_1001
010_1010_1010
010_1010_1011
Figure 16-9 Reception Flowchart
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010

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