HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 727

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.5
Usage Notes
(1) Reset
The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All the
registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data
(MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message
data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization
must always be carried out after a reset or a transition to hardware standby mode or software
standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery from
software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if
HCAN interrupts are set as enabled by the interrupt controller without this flag having been
cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be cleared during
initialization.
(2) HCAN sleep mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in
HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release.
Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode.
(3) Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8,2,1) is not
set by reception completion, transmission completion, or transmission cancellation for the set
mailboxes.
(4) Error counters
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set.
(5) Register access
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
(6) HCAN medium-speed mode
HCAN registers cannot be read or written to in medium-speed mode.
REJ09B0103-0800 Rev. 8.00
Page 677 of 1458
May 28, 2010