HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 763

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Note: The H8S/2635 Group is not equipped with a DTC.
19.1
The chip has an on-chip motor control PWM (pulse width modulator) with a maximum capability
of 16 pulse outputs.
19.1.1
Features of the motor control PWM are given below.
• Maximum of 16 pulse outputs
• Buffered duty registers
• 0% to 100% duty
• Five operating clocks
• High-speed access via internal 16-bit-bus
• Two interrupt sources
• Automatic transfer of register data
• Module stop mode
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ Two 10-bit PWM channels, each with eight outputs.
⎯ Each channel is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR).
⎯ Duty and output polarity can be set for each output.
⎯ Duty registers (PWDTR) are provided with buffer registers (PWBFR), with data
⎯ Channel 1 has four duty registers and four buffer registers.
⎯ Channel 2 has eight duty registers and four buffer registers.
⎯ A duty cycle of 0% to 100% can be set by means of a duty register setting.
⎯ There is a choice of five operating clocks (φ, φ/2, φ/4, φ/8, φ/16).
⎯ High-speed access is possible via a 16-bit bus interface.
⎯ An interrupt can be requested independently for each channel by a cycle register compare
⎯ Block transfer and one-word data transfer are possible by activating the data transfer
⎯ As the initial setting, PWM operation is halted. Register access is enabled by clearing
transferred automatically every cycle.
match.
controller (DTC).
module stop mode.
Overview
Features
Section 19 Motor Control PWM Timer
Section 19 Motor Control PWM Timer
Page 713 of 1458

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