HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 785

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
19.5
Contention between Buffer Register Write and Compare Match
If a PWBFR write is performed in the state immediately after a cycle register compare match, the
PWM output does not change, but as the duty register is also rewritten at the same time as the
buffer register, normal PWM output will not be achieved.
If a PWBFR write is performed in the state immediately after a cycle register compare match, the
buffer register and duty register are overwritten. PWM output changed by the cycle register
compare match is not changed in the overwrite of the duty register due to contention. This may
result in unanticipated duty output. In the case of channel 2, the duty register used as the transfer
destination is selected by the TDS bit of the buffer register when an overwrite of the duty register
occurs due to contention. This can also result in an unintended overwrite of the duty register.
Buffer register rewriting must be completed before automatic transfer by the DTC * (data transfer
controller), exception handling due to a compare match interrupt, or the occurrence of a cycle
register compare match on detection of the rise of CMF (compare match flag) in PWCR.
Note: * The DTC is not implemented in the H8S/2635 and H8S/2634.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Address
Write signal
PWCNT
(lower 10 bits)
PWBFR
PWDTR
PWM output
CMF
φ
Usage Note
Figure 19-12 PWM Channel 1 Operation
T
1
Buffer register address
N
Compare match
T
W
T
W
N
T
0
2
M
M
Section 19 Motor Control PWM Timer
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