HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 8

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
2.6.3 Table of
Instructions Classified
by Function
Table 2-3 Instructions
Classified by Function
2.8.1 Overview
Figure 2-14
Processing States
2.8.3 Exception-
Handling State
3.4 Pin Functions in
Each Operating Mode
Table 3-3 Pin
Functions in Each
Mode
4.1.1 Exception
Handling Types and
Priority
4.2.2 Reset Sequence
Figure 4-2 Reset
Sequence (Modes 6
and 7)
Page viii of l
Page
50
63
65
86
93
97
Revision (See Manual for Details)
Table amended
Figure amended
Description amended
The exception-handling state is a transient state that occurs
when the CPU alters the normal processing flow due to a reset,
trace, interrupt, or trap instruction. The CPU fetches a start
address (vector) from the exception vector table and branches
to that address.
Table amended
Description amended
As table 4-1 indicates, exception handling may be caused by a
reset, trace, direct transition*, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1.
Figure amended
Port
Port F
Type
Bit-
manipulation
instructions
φ
PF7
PF6 to PF4
PF3
Instruction
BOR
BIOR
Exception-handling
The CPU and all on-chip supporting modules have been
initialized and are stopped.
A transient state in which the CPU changes the normal
processing flow in response to a reset, trace, interrupt,
or trap instruction.
Reset state
state
Mode 4
P/C*
C
P/C*
Size*
B
B
1
Function
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
C ∨ [ ¬ (<bit-No.> of <EAd>) ] → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
Mode 5
P/C*
C
P*/C
Vector
fetch
REJ09B0103-0800 Rev. 8.00
Mode 6
P/C*
C
P*/C
Prefetch of first program
instruction
Mode 7
P*/C
P
May 28, 2010