HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 953

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
22A.1 Overview
The chip has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
22A.1.1 Block Diagram
Figure 22A-1 shows a block diagram of the clock pulse generator.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
EXTAL
XTAL
OSC1
OSC2
Legend:
LPWRCR:
SCKCR:
Note:
*
*
*
Low-power control register
System clock control register
Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and
W-mask versions only.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
oscillator
Subclock
oscillator
System
clock
Figure 22A-1 Block Diagram of Clock Pulse Generator
Section 22A Clock Pulse Generator
(×1, ×2, ×4)
Generation
PLL circuit
Waveform
LPWRCR
Circuit
WDT1 count clock
STC1, STC0
φSUB
selection
circuit
Clock
System clock
to φ pin
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
clock divider
Medium-
speed
supporting modules
Internal clock to
φ/2 to
Section 22A Clock Pulse Generator
φ/32
φ
selection
SCKCR
master
circuit
clock
Bus
Bus master clock
to CPU and DTC
SCK2 to SCK0
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