HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 990
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 23A Power-Down Modes
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
23A.6 Software Standby Mode
23A.6.1 Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of
the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, Motor control, PWM, HCAN and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
23A.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt
• Clearing with the RES pin
Page 940 of 1458
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
[HD64F2636F, HD64F2638F, HD6432636F,
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
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