HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet
HD6417708RF100A
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HD6417708RF100A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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SH7708 Series 32 SH7708, SH7708S, SH7708R Hardware Manual Renesas SuperH™ RISC engine Rev.9.0 2000.09 ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The SH7708, SH7708S, and SH7708R(SH7708 Series) use a RISC (reduced instruction set computer) type CPU to achieve high-performance computational processing. Also incorporating the peripheral functions required for system configuration plus power-down features essential for microcontroller application systems, the SH7708 Series ...
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Revisions and Additions in this Edition Page Item 338, 339 12.4.3 Usage Note about Periodic Interrupt on RTC 494 Figure 16.65 Output Load Circuits 554 Figure 17.65 Output Load Circuits Description New section added [Former Edition] The mark of VRER ...
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Section 1 Overview and Pin Functions 1.1 SH7708 Series Features.................................................................................................... 1.2 Block Diagram................................................................................................................... 1.3 Pin Description .................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 SH7708 Series Pin Functions ............................................................................... Section 2 CPU ....................................................................................................................... 13 2.1 Register Configuration ..................................................................................................... 13 2.1.1 Privileged Mode ...
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Page Management Information ............................................................................ 65 3.4 MMU Functions ................................................................................................................ 66 3.4.1 MMU Hardware Management ............................................................................. 66 3.4.2 MMU Software Management............................................................................... 66 3.4.3 MMU Instruction (LDLTB) ................................................................................. 67 3.4.4 Avoiding Synonym Problems .............................................................................. 68 3.5 MMU Exceptions .............................................................................................................. 70 3.5.1 ...
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Features ................................................................................................................ 97 5.1.2 Cache Structure .................................................................................................... 97 5.1.3 Register Configuration ......................................................................................... 99 5.2 Register Description .......................................................................................................... 99 5.2.1 Cache Control Register (CCR)............................................................................. 99 5.3 Cache Operation ................................................................................................................ 100 5.3.1 Searching the Cache ............................................................................................. 100 5.3.2 Read Access.......................................................................................................... 102 ...
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Break Conditions and Register Settings ............................................................... 125 7.2 UBC Register Functions.................................................................................................... 126 7.2.1 Break Address Register A (BARA) ..................................................................... 126 7.2.2 Break Address Register B (BARB)...................................................................... 126 7.2.3 Break ASID Register A (BASRA) ....................................................................... 127 7.2.4 Break ASID Register ...
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Transition to Hardware Standby Mode ................................................................ 153 8.7.2 Canceling Hardware Standby Mode .................................................................... 154 8.7.3 Hardware Standby Mode Timing ......................................................................... 154 Section 9 On-Chip Oscillation Circuits 9.1 Overview............................................................................................................................ 157 9.1.1 Features ................................................................................................................ 157 9.2 Overview of the CPG ........................................................................................................ ...
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Register Configuration ......................................................................................... 192 10.1.5 Area Overview...................................................................................................... 193 10.1.6 PCMCIA Support ................................................................................................. 196 10.2 BSC Registers.................................................................................................................... 200 10.2.1 Bus Control Register 1 (BCR1)............................................................................ 200 10.2.2 Bus Control Register 2 (BCR2)............................................................................ 203 10.2.3 Wait State Control Register 1 (WCR1)................................................................ 204 ...
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Timer Start Register (TSTR)................................................................................ 305 11.2.3 Timer Control Register (TCR) ............................................................................. 306 11.2.4 Timer Constant Register (TCOR) ........................................................................ 309 11.2.5 Timer Counters (TCNT)....................................................................................... 310 11.2.6 Input Capture Register (TCPR2).......................................................................... 311 11.3 TMU Operation ................................................................................................................. 312 11.3.1 Overview .............................................................................................................. 312 ...
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Reading the Time ................................................................................................. 335 12.3.4 Alarm Function .................................................................................................... 336 12.3.5 Crystal Oscillator Circuit...................................................................................... 337 12.4 Usage Notes ....................................................................................................................... 338 12.4.1 Flag Clearing ........................................................................................................ 338 12.4.2 Register Writes during RTC Count ...................................................................... 338 12.4.3 Usage Note about Periodic Interrupt ...
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Pin Connections.................................................................................................... 405 14.3.3 Data Format.......................................................................................................... 406 14.3.4 Register Settings................................................................................................... 407 14.3.5 Clock .................................................................................................................... 409 14.3.6 Data Transmission and Reception........................................................................ 412 14.4 Usage Notes ....................................................................................................................... 418 14.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode.................... 418 14.4.2 Retransmission ...
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Basic Timing ........................................................................................................ 512 17.3.5 Burst ROM Timing .............................................................................................. 515 17.3.6 DRAM Timing ..................................................................................................... 518 17.3.7 Synchronous DRAM Timing................................................................................ 528 17.3.8 Pseudo-SRAM Timing ......................................................................................... 539 17.3.9 PCMCIA Timing.................................................................................................. 544 17.3.10 Peripheral Module Signal Timing ........................................................................ 551 17.3.11 AC Characteristics ...
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Section 1 Overview and Pin Functions 1.1 SH7708 Series Features The SH7708, SH7708S, and SH7708R(SH7708 Series) are 32-bit RISC (reduced instruction set computer) microcomputers, featuring object code upward-compatibility with SH-1 and SH-2 microcomputers. The SH7708R is completely pin compatible with ...
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Table 1.1 SH7708 Series Features Item Features CPU Original Hitachi SuperH RISC engine architecture 32-bit internal data bus General-register machine Sixteen 32-bit general registers (eight 32-bit bank registers) Five 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward ...
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Table 1.1 SH7708 Series Features (cont) Item Features Memory 4 Gbytes of address space, 256 address spaces (8-bit ASID) management Supports single virtual memory mode and multiple virtual memory mode unit (MMU) Paging system Supports multiple page sizes ...
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Table 1.1 SH7708 Series Features (cont) Item Features Bus state Supports external memory access controller 32/16/8-bit external data bus (BSC) Physical address space divided into seven areas, each a maximum 64 Mbytes, with the following features settable for each area: ...
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... Voltage SH7708 3.3V 0.3V SH7708S 3.3V 0.3V SH7708R 3.15-3.6V (typ.) Operation Mask Frequency Version Model 60MHz — HD6417708F60 60MHz — HD6417708SF60 — HD6417708STF60 100MHz — HD6417708RF100 A-mask HD6417708RF100A Package 144-pin Plastic LQFP (FP-144F) 144-pin Plastic TQFP (TFP-144) 144-pin Plastic L-QFP (FP-144F) 5 ...
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Block Diagram Figure 1.1 shows a block diagram of the SH7708 Series. Multiplier MMU (memory management unit) Mixed instruction/ data TLB Cache controller Mixed instruction/ data cache memory External bus Figure 1.1 SH7708 Series Block Diagram 6 CPU Interrupt ...
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Pin Description 1.3.1 Pin Arrangement CS5/CE1A CS4 CS3 CS2 CS1 CS0 Vss Vcc WE3/DQMUU/ICIOWR WE2/DQMUL/ICIORD CASHH/CAS2H CASHL/CAS2L 120 Vss Vcc WE1/DQMLU WE0/DQMLL CASLH CASLL/CAS/OE Vss Vcc RAS/CE 130 MD5/RAS2 CKE WAIT Vss TCLK Vcc (RTC XTAL2 EXTAL2 ...
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SH7708 Series Pin Functions Table 1.2 SH7708 Series Pin Functions No. Terminal 1 D27 2 D26 3 D25 4 D24 5 D23/Port7 D22/Port6 9 D21/Port5 10 D20/Port4 11 D19/Port3 12 D18/Port2 13 ...
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Table 1.2 SH7708 Series Pin Functions (cont) No. Terminal ...
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Table 1.2 SH7708 Series Pin Functions (cont) No. Terminal 61 A16 62 A17 63 A18 64 A19 65 A20 66 A21 67 A22 A23 71 A24 72 A25 (PLL1)* SS ...
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Table 1.2 SH7708 Series Pin Functions (cont) No. Terminal IRL2 91 IRL1 92 IRL0 93 IOIS16 94 IRQOUT 95 BACK 96 97 STATUS1 98 STATUS0 99 NC 100 V SS 101 CKIO 102 V CC 103 MD4/CE2B 104 MD3/CE2A BS ...
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Table 1.2 SH7708 Series Pin Functions (cont) No. Terminal 122 V CC WE1/DQMLU 123 WE0/DQMLL 124 CASLH 125 CASLL/CAS/OE 126 127 V SS 128 V CC RAS/CE 129 130 MD5/RAS2 131 CKE WAIT 132 133 V SS 134 TCLK 3 ...
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Register Configuration 2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7708 Series normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is ...
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Notes functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. 2. Banked register Figure 2.1 User Mode Register Configuration BANK0 BANK0* 2 ...
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R0_BANK1* 2 R1_BANK1* 2 R2_BANK1* 2 R3_BANK1* 2 R4_BANK1* 2 R5_BANK1* 2 R6_BANK1* 2 R7_BANK1 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC , ...
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Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type General registers Control registers System registers Note: Initialized by a power-on reset or manual reset. 2.1.2 General Registers There are 16 general registers, designated ...
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System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the ...
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SSR 31 SPC 31 GBR 31 VBR 0––––––––––––––––––––––––––––0 MD: Processor operation mode bit: Indicates the processor operation mode as follows: MD =1: Privileged mode User mode MD ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded ...
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Address Address Address Address A Byte0 Byte1 Byte2 Byte3 Address Word0 Address Big-endian mode Figure 2.7 Byte, Word, and Longword Alignment 2.3 Instruction Features 2.3.1 ...
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T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Register direct Rn Effective address is register Rn. (Operand is ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method Register @(disp:4, Effective address is register Rn contents with indirect with Rn) 4-bit displacement disp added. After disp is displacement zero-extended multiplied ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method PC-relative @(disp:8, Effective address is register PC contents with with PC) 8-bit displacement disp added. After disp is displacement zero-extended multiplied by ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method PC-relative Rn Effective address is sum of register PC and Rn contents. Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR ...
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Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register ...
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Table 2.3 Instruction Formats (cont) Instruction Format 15 nm format xxxx nnnn mmmm 15 md format xxxx xxxx mmmm 15 nd4 format xxxx xxxx Source Operand 0 mmmm: register direct xxxx mmmm: register direct mmmm: register indirect with post- increment ...
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Table 2.3 Instruction Formats (cont) Instruction Format nmd 15 format xxxx nnnn mmmm d format 15 xxxx xxxx d12 format 15 xxxx dddd nd8 format 15 xxxx nnnn 15 i format xxxx xxxx ni format 15 xxxx nnnn Note: In ...
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Instruction Set 2.4.1 Instruction Set Classified by Function The SH7708 Series instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP ...
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Table 2.4 Classification of Instructions (cont) Operation Classification Types Code Arithmetic 21 MUL operations MULS (cont) MULU NEG NEGC SUB SUBC SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL ...
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Table 2.4 Classification of Instructions (cont) Operation Classification Types Code Branch BRA BRAF BSR BSRF JMP JSR RTS System 15 CLRT control CLRMAC CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: ...
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Table 2.5 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST mnemonic Instruction MSB LSB code Operation , (xx) M/Q/T & <<n, >>n Privileged mode Execution cycles T bit Note: Scaling ( performed according to ...
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Table 2.6 lists the SH7708 Series data transfer instructions Table 2.6 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn (disp MOV.W @(disp,PC),Rn extension (disp MOV.L @(disp,PC),Rn Rm MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn Rm MOV.L Rm,@Rn (Rm) MOV.B ...
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Table 2.6 Data Transfer Instructions (cont) Instruction Operation Rm MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn extension (R0 + Rm) MOV.W @(R0,Rm),Rn extension (R0 + Rm) MOV.L @(R0,Rm),Rn R0,@(disp,GBR) R0 MOV.B R0,@(disp,GBR) R0 MOV.W R0,@(disp,GBR) R0 MOV.L @(disp,GBR),R0 (disp + ...
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Table 2.7 lists the SH7708 Series arithmetic instructions. Table 2.7 Arithmetic Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry ADDV Rm,Rn Overflow If R0 ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation Signed operation of DMULS.L Rm, MACL 32 Unsigned operation of DMULU.L Rm, MACL 32 Rn – else 0 A byte ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation 0–Rm NEG Rm,Rn 0–Rm–T NEGC Rm,Rn Borrow Rn–Rm SUB Rm,Rn Rn–Rm–T SUBC Rm,Rn Borrow Rn–Rm SUBV Rm,Rn Underflow Note: * The normal number of execution cycles is shown. The value in parentheses is ...
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Table 2.8 lists the SH7708 Series logic operation instructions. Table 2.8 Logic Operation Instructions Instruction Operation Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & imm AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm NOT Rm,Rn Rn ...
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Table 2.9 lists the SH7708 Series shift instructions. Table 2.9 Shift Instructions Instruction Operation T Rn ROTL Rn LSB ROTR ROTCL ROTCR << Rm SHAD Rm,Rn Rn < ...
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Table 2.10 lists the SH7708 Series branch instructions. Table 2.10 Branch Instructions Instruction Operation disp BF label nop (where label is disp + PC) Delayed branch BF/S label ...
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Table 2.11 lists the SH7708 Series system control instructions. Table 2.11 System Control Instructions Instruction Operation 0 MACH, MACL CLRMAC 0 S CLRS 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm SSR ...
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Table 2.11 System Control Instructions (cont) Instruction Operation (Rm) LDC.L @Rm R4_BANK (Rm) LDC.L @Rm R5_BANK (Rm) LDC.L @Rm R6_BANK (Rm) LDC.L @Rm R7_BANK Rm MACH LDS Rm,MACH ...
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Table 2.11 System Control Instructions (cont) Instruction Operation R4_BANK STC R4_BANK,Rn R5_BANK STC R5_BANK,Rn R6_BANK STC R6_BANK,Rn R7_BANK STC R7_BANK,Rn Rn–4 STC.L SR,@–Rn Rn–4 STC.L GBR,@–Rn Rn–4 STC.L VBR,@–Rn Rn–4 STC.L SSR,@–Rn Rn–4 STC.L SPC,@–Rn Rn–4 STC.L R0_BANK, @–Rn Rn–4 ...
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Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: • When there is contention between an instruction fetch and data access • When ...
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Instruction Code Map Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map Instruction Code Fx: 0000 MD: 00 MSB LSB 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC SR,Rn 0000 Rn ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 0100 Rn Fx 0000 SHLL Rn 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L MACH,@-Rn 0100 Rn 00MD 0011 STC.L SR,@-Rn 0100 Rn ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 11MD imm/disp 1001 Rn disp MOV.W @(DISP:8,PC),RN 1010 ...
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Processor States and Processor Modes 2.5.1 Processor States The SH7708 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The reset ...
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From any state except hardware standby mode when RESET = 0 and BREQ = 1 Power-on reset Interrupt Bus-released state Bus Bus request request clearance Sleep mode RESET = 0, BREQ = 1 Note: * Driving the ...
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Usage Note In the SH7708R, operations may not be performed correctly when the following sequences are executed with the cache on. Address Instruction 4n MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+2 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+4 STS(.L)/LDS(.L) ...
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7708 Series has an on-chip memory management unit (MMU) that implements address translation. The SH7708 Series features a resident translation lookaside buffer (TLB) that caches information for user-created address ...
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MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by ...
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Process 1 Physical memory Process Process 1 Process 2 Process 3 Process 1 Physical memory (1) Process 1 Physical memory Process 2 Process 3 (3) Figure 3.1 ...
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SH7708 Series MMU Virtual Address Map: The SH7708 Series uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In privileged mode, there are ...
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H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) H'7F000000 On-chip RAM space H'80000000 0.5-Gbyte fixed physical space, cacheable (write-through: SH7708) (write-back/write-through: SH7708S, SH7708R) H'A0000000 0.5-Gbyte fixed physical space, non-cacheable H'C0000000 0.5-Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5-Gbyte control space, non-cacheable H'FFFFFFFF Privileged ...
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Physical Address Space: The SH7708 Series supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller, for details. Single Address Translation: When the MMU is ...
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Address Space Identifier (ASID): When multiple processes run in parallel sharing the same virtual address space and the processes have unique address translation tables, the virtual space can be multiplexed. The ASID is 8 bits in length and is held ...
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Register Description There are five registers for MMU processing. These are all peripheral module registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address. These registers consist ...
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The MMU registers are shown in figure 3. Virtual address causing TLB-related 31 0: Reserved bits (except MMUCR): Always read as 0. Writing is ignored. (MMUCR) :Except bit 3 is read as 0. Bit 3 is ...
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TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the ...
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Virtual address (1-kbyte page) 31 Virtual address (4-kbyte page) (15) (2) VPN (31–17) VPN (11–10) ASID VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual ...
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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits are used as the index number regardless of the page size. The index number can be generated ...
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Virtual address Index 0 VPN(31–17) VPN(11–10) 31 Address array 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual ...
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The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes ( but not when there is sharing (SH = 1). When ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., ...
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MMU Functions 3.4.1 MMU Hardware Management MMU hardware management is of the following two kinds. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR ...
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MMU Instruction (LDLTB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR ...
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Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded ...
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When using a 4-kbyte page Virtual address VPN Physical address PPN When using a 1-kbyte page Virtual address 31 VPN Physical address 31 PPN Figure 3.10 Synonym Problem 0 ...
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MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry ...
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If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return ...
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TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid ...
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Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is ...
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No VPNs match? TLB miss exception PR check 00/01 W R/W? TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.11 MMU Exception Generation Flowchart 74 Start and (MMUCR. ...
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Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in instruction fetch mode. : Exception source stage IF = Instruction fetch ID = Instruction decode EX = Instruction ...
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Figure 3.13 shows the MMU exception signals in data access mode Exception source stage : Stage cancellation for instruction that has begun execution IF = Instruction fetch ID = Instruction decode EX = ...
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Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in privileged mode using the MOV instruction. The TLB is assigned to the P4 area in virtual address space. ...
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Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. These are specified in the general ...
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TLB Address Array Access Read access 31 Address field 11110010 31 Data field Write access 31 Address field 11110010 31 Data field VPN: Virtual page number V: Valid bit A: Association bit W: Way (00: Way 0, 01: Way ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exceptions are deviations from normal program execution that require special handling. The processor responds to an exception by aborting execution of the current instruction (execution is allowed to continue to completion in ...
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A basic exception processing sequence consists of the following operations: The contents of the PC and SR are saved in the SPC and SSR, respectively. The block (BL) bit set to 1, masking any subsequent exceptions. The ...
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Table 4.2 Vectored Exception Events Exception Current Type Instruction Exception Event Reset Aborted Power-on Manual reset General Aborted Address error exception and retried (instruction access) events TLB miss (instruction access) TLB invalid (instruction access) TLB protection violation (instruction access) Reserved ...
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Table 4.2 Vectored Exception Events (cont) Exception Current Type Instruction Exception Event General Completed Nonmaskable interrupt interrupt requests External hardware interrupt Peripheral module interrupt Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest. ...
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Pipeline Sequence: Instruction n Instruction Instruction Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and RIE (instruction simultaneous detection Handling Order: TLB miss (instruction n) Re-execution of instruction ...
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Exception Codes Table 4.3 lists the exception codes written to bits 11–0 of the ...
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Table 4.3 Exception Codes (cont) Exception Type General interrupt requests (cont) Note: Exception codes H'120, H'140, and H'3E0 are reserved. 4.2.5 Exception Request Masks When the BL bit cleared to 0, exceptions and interrupts are accepted. If ...
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Returning from Exception Handling The RTE instruction is used to return from exception handling. When RTE is executed, the SPC value is set in the PC, and the SSR value in SR, and the return from exception handling is ...
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Exception Handler Operation 4.4.1 Reset The reset sequence is used to power up or restart the SH7708 Series from the initialization state. The RESET signal is sampled every clock cycle, and in the case of a power-on reset, all ...
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The RB bit set encoded value identifying the exception event is written to bits 11–0 of the EXPEVT register. Instruction execution jumps to the vector location designated by either the sum of the vector ...
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General Exceptions TLB miss exception Conditions: Comparison of TLB addresses shows no address match Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in ...
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TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR Privileged mode 00 Only read enabled 01 Read/write enabled 10 Only read enabled 11 Read/write enabled Operations: The virtual address (32 bits) ...
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Reserved instruction exception Conditions: a. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R) b. When a privileged instruction not in ...
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Interrupts NMI Conditions: NMI pin edge detection Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC and SSR, respectively. H'01C0 is set in INTEVT. The BL, MD, and RB bits in ...
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Cautions Return from exception handling Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit before restoring them. Issue an RTE instruction. ...
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96 ...
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Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity Selectable: Structure Instruction/data mixed, 4-way set associative (2-way set associative in RAM mode) Line size 16 bytes Number of entries 128 ...
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Address array (ways 0–3) Entry Address Entry 1 • • • • Entry 127 22) bits Address Array: The V bit indicates whether the entry data is valid. When the V bit ...
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In RAM mode, two ways are used as cache (way 0 and way 1). Bit 5 of the LRU bits indicates which way replaced. When bit way replaced. When bit ...
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RA: RAM bit. Indicates the cache operation mode kbytes cache/4 kbytes cache (RAM mode kbytes cache (normal mode) 0: Always set to 0 when setting the register. CF: ...
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Virtual address Entry selection Ways 0– MMU 1 127 Physical address CMP0 CMP1 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.3 ...
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Read Access Read Hit read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry ...
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PA (31–4) PA (31–4): Longword 0–3: Figure 5.4 Write-Back Buffer Configuration 5.3.5 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by the SH7708 Series and another device ...
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In the address field, specify the entry address for selecting the entry (bits 10–4), W for selecting the way (bits 12–11 way way way way 3 in normal mode ...
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RAM mode), and H'F1 to indicate data array access (bits 31–24). Both reading and writing use ...
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Usage Examples 5.5.1 Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the address tag specified by the write data is compared to the address ...
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle ...
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Block Diagram Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRL3–IRL0 4 (Interrupt request) TMU (Interrupt request) RTC (Interrupt request) SCI (Interrupt request) WDT (Interrupt request/ REF refresh request) TMU: Timer unit RTC: Realtime clock unit ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Nonmaskable interrupt input pin Interrupt input pins Bus request output pin 6.1.4 Register Configuration The INTC has the three registers listed in table 6.2. Table ...
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NMI Interrupts The NMI interrupt has the highest priority level of 16 always accepted unless the BL bit in the status register in the CPU is set to 1, and is edge-detected. In sleep or standby mode, ...
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IRL3–IRL0 Pins and Interrupt Levels Table 6.3 IRL3 IRL2 IRL1 ...
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On-Chip Supporting Module Interrupts On-chip supporting module interrupts are generated by the following five modules: Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Bus state controller (BSC) Watchdog timer (WDT) Not every interrupt source is assigned a ...
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When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they are handled according to the default order listed in table 6.4. Updating of interrupt priority level setting ...
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Table 6.4 Interrupt Exception Vectors and Rankings (cont) INTEVT Interrupt Source Code 3 RTC ATI* H'480 4 RTC PRI* H'4A0 5 RTC CUI* H'4C0 6 SCI ERI* H'4E0 7 SCI RXI* H'500 8 SCI TXI* H'520 9 SCI TEI* H'540 ...
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INTC Registers 6.3.1 Interrupt Priority Registers A and B (IPRA, IPRB) Interrupt priority registers A and B (IPRA and IPRB) are 16-bit read/write registers that set priority levels from for on-chip supporting module interrupts. These registers ...
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Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register is initialized by a ...
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INTC Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Program execution state Interrupt No generated? Yes (SR (sleep or standby mode)? Yes No NMI? Yes Yes IRQOUT = low Set interrupt cause in INTEVT Save SR to SSR; save PC to SPC Set BL/MD/RB ...
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Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT. The code in INTEVT can be used as a branch-offset for ...
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Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 6.6. Figure ...
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Table 6.6 Interrupt Response Time (cont) Item NMI Response Total (5 time + 0.5 + 0.5 Minimum 6.5 2 case* Maximum case* Icyc: Duration of one cycle of internal clock supplied to CPU, etc. ...
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Icyc + 0 Pcyc IRL Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler IF: Instruction fetch ... Instruction is fetched from memory in which program is stored. ID: Instruction decode ... ...
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Section 7 User Break Controller (UBC) 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling programs to be debugged in the chip alone, without ...
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Access control BBRA: Break bus cycle register A BARA: Break address register A BASRA: Break ASID register A BAMRA: Break address mask register A BBRB: Break bus cycle register B BARB: Break address register B BASRB: Break ASID register B ...
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Register Configuration Table 7.1 shows the user break controller registers. Table 7.1 UBC Registers Channel Register A BARA BASRA BAMRA BBRA B BARB BAMRB BASRB BBRB BDRB BDMRB Common BRCR Notes: 1. Value is retained in standby mode. 2. ...
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Sequential use of channels A and B is set in the SEQ bit of the BRCR. When sequential use is designated, a user break occurs when the channel B conditions are matched after matching of channel A conditions. 6. ...
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Break ASID Register A (BASRA) Bit: 7 Bit name: BASA7 Initial value: — R/W: R/W Break ASID register A (BASRA) specifies the ASID that serves as the break condition for channel compared to the ASID field ...
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Bits 1 and 0—Break Address Mask A1 and A0 (BAMA1 and BAMA0): These bits indicate which of the channel A break address bits 31–0 (BAA31–BAA0) set in BARA are masked. Bit 1: BAMA1 Bit 0: BAMA0 ...
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Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether to break channel A on instruction fetch and/or data access cycles. Bit 5: IDA1 Bit 4: IDA0 Bits 3 ...
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Break Data Register B (BDRB) Bit: 31 Bit name: BDB31 Initial value: — R/W: R/W Bit: 23 Bit name: BDB23 Initial value: — R/W: R/W Bit: 15 Bit name: BDB15 Initial value: — R/W: R/W Bit: 7 Bit name: ...
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Break Data Mask Register B (BDMRB) Bit: 31 Bit name: BDM31 Initial value: — R/W: R/W Bit: 23 Bit name: BDM23 Initial value: — R/W: R/W Bit: 15 Bit name: BDM15 Initial value: — R/W: R/W Bit: 7 Bit ...
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Break Control Register (BRCR) Bit: 15 Bit name: CMFA Initial value: 0 R/W: R/W Bit: 7 Bit name: DBEB Initial value: 0 R/W: R/W The break control register (BRCR 16-bit read/write register that controls user breaks. BRCR: ...
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Bit 10—PC Break Select A (PCBA): Selects whether to place the channel A instruction fetch cycle break before or after instruction execution. Bit 10: PCBA Description 0 Places the channel A PC break before instruction execution. 1 Places the channel ...
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UBC Operation 7.3.1 User Break Operation Flow The flow from break condition setting to user break trap processing is as follows the break conditions, set the break address in the break address register for the relevant channel ...
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Instruction Fetch Cycle Break 1. Making an instruction fetch/read/word setting made in the break bus cycle register (BBRA/BBRB) enables an instruction fetch cycle to be set as a break condition. In this case, pre- or post-execution of the instruction ...
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Data Access Cycle Break 1. In the case of a data access cycle break, the bits used for comparison with the address bus depend on the break bus cycle register (BBRA/BBRB) operand size specification, as follows: Operand size Not ...
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Saved Program Counter (PC) Value 1. When instruction fetch (pre-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt handling is the address of the instruction for which the break ...
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Examples of Use Register settings, set conditions, and states in which the set conditions are matched, are as follows: 1. Instruction fetch cycle break condition setting (independent channel A and B conditions) BRCR = H'0400: Independent channel A and ...
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ASID = H'70, after execution of the instruction at address H'00037226 with ASID = H'80. 3. Data access cycle break condition setting BRCR = H'0080: Independent channel A and B conditions, data break enable Channel A: BASRA = H'80: BARA ...
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Cautions 1. If pre-execution is specified for one channel and post-execution for the other for the same address, a pre-execution break will be generated but the condition match flag will be set for both channels not set ...
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Section 8 Power-Down Modes 8.1 Overview In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes The SH7708 Series have the following power-down modes: 1. Sleep mode 2. Standby ...
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Table 8.1 Power-Down Modes State Transition Mode Conditions CPG CPU Sleep Execute SLEEP Runs Halts mode instruction with STBY bit cleared STBCR Standby Execute SLEEP Halts Halts mode instruction with STBY bit set STBCR ...
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Pin Configuration Table 8.3 lists the pins used for the power-down modes. Table 8.3 Pin Configuration Processing Status 1 Pin (STATUS1) High Low Note: The “normal operation” status applies during refresh cycles even in sleep mode. 8.2 Register Description ...
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Bit 2—Module Standby 2 (MSTP2): Specifies halting the clock supply to the timer unit TMU (an on-chip supporting module). When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted. Bit 2: MSTP2 ...
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Sleep Mode 8.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP ...
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Table 8.4 Register States in Standby Mode Module Interrupt controller Break controller Bus state controller On-chip clock pulse generator Timer unit Realtime clock The procedure for moving to standby mode is as follows: 1. Clear the TME bit in the ...
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Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin. 8.4.3 Clock Pause ...
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Clearing the Module Standby Function The module standby function can be cleared by clearing the MSTP2–MSTP0 bits power-on reset or manual reset. 8.6 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 ...
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Power-On Reset (Clock Modes 3 and 4): CKIO RESET Normal STATUS Figure 8.2 Power-On Reset (Clock Mode 3 and 4) STATUS Output Manual Reset: CKIO RESET Normal STATUS Note: * During manual reset, STATUS becomes HH (reset) and the internal ...
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Timing for Canceling Standbys Standby to Interrupt: Oscillation stops CKIO Normal STATUS Figure 8.4 Standby to Interrupt STATUS Output Standby to Power-On Reset: Oscillation stops CKIO RESET* STATUS Normal Note: When standby mode is cleared with a power-on reset, ...
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Standby to Manual Reset: Oscillation stops CKIO RESET* STATUS Normal Note: When standby mode is cleared with a manual reset, the WDT does not count. Keep RESET low during the PLL’s oscillation settling time. Figure 8.6 Standby to Manual Reset ...
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Sleep to Power-On Reset: CKIO RESET* STATUS Normal Note: When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESET low during the PLL’s oscillation settling time. *: Undefined Figure 8.8 Sleep to Power-On Reset STATUS Output Sleep ...
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Hardware Standby Mode The hardware standby mode is provided only in the SH7708S and SH7708R. This mode is not supported in emulator. 8.7.1 Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby ...
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Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESET pin is low and the BREQ pin is high, clock oscillation is started. Hold ...
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CKIO CA RESET STATUS Standby WDT operation 2 Rcyc or more Figure 8.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation Normal Standby on Standby Mode Cancellation) Reset Undefined Bcyc 155 ...
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156 ...
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Section 9 On-Chip Oscillation Circuits 9.1 Overview The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. The watchdog timer (WDT single-channel timer that counts the clock settling time and is used ...
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Overview of the CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S) and figure 9.2(SH7708R). CAP1 CKIO Cycle = Bcyc CAP2 Crystal XTAL oscillator EXTAL MD2 MD1 MD0 ...
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CAP1 CKIO Cycle = Bcyc CAP2 Crystal XTAL oscillator EXTAL MD2 MD1 MD0 FRQCR: Frequency control register Figure 9.2 Block Diagram of Clock Pulse Generator(SH7708R) The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 ...
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Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL pins. It operates according to the clock operating mode setting. 4. Divider 1: Divider 1 generates a clock at the operating ...
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CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 Clock Pulse Generator Pins and Functions Pin Name Symbol Mode control MD0 pins MD1 MD2 Crystal I/O pins XTAL (clock input pins) EXTAL Clock I/O ...
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Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes Pin Values ...
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Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied PLL circuit 2 before being supplied inside the SH7708 Series, allowing a low-frequency external clock to be used. An input clock ...
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S) FRQCR Register Mode Value PLL1 0 H'0102 H'0101 H'0100 H'0112 H'0111 H'0115 ON ...
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S) (cont) FRQCR Register Mode Value PLL1 2 5* H'0102 OFF H'0101 OFF H'0100 OFF H'01d1 H'01d0 H'01d4 H'01d5 ON ...
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Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) Clock Mode FRQCR PLL1 0 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 ...
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Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont) Clock Mode FRQCR PLL1 3 H’81C0 H’81C1 H’C1C0 H’C1C1 H'01E0 H’01E1 ON ( ...
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Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont) Clock Mode FRQCR PLL1 7 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 ON ( ...
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Do not set the internal clock frequency lower than the CKIO pin frequency. 5. The frequency of the peripheral clock (P ) becomes: The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, ...
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Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR 16-bit read/write register used to specify whether a clock is output from the CKIO pin, the on/off state of PLL circuit 1, PLL standby, the ...
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Bit 7—PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid in clock operating modes 3–6. PLL circuit 1 goes on when the clock operating mode is 0– irrespective of the value ...
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Bits 1 and 0—Peripheral Clock Frequency Division Ratio (PFC1, PFC0): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO ...
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Bit 14: IFC2 Bit 2: IFC1 Note: Do not set the interunal clock frequency lower then the CKIO frequency. Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC): These bits specify ...
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Bit 6: PSTBY Description 0 PLL is not in standby mode. 1 PLL is in standby mode. 9.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of ...
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PLL Standby Function 9.6.1 Overview of the PLL Standby Function When operating in clock modes 3 and 4, the internal clock can be controlled by turning the PLL1 circuit on and off. A long oscillation settling time is required, ...
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In clock modes 3 and 4, the SH7708 Series cannot go to standby mode while PLL circuit 1 is on. Always set PSTBY and PLLEN stop PLL circuit 1 before going to standby mode. 4. When ...
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Overview of the Watchdog Timer (WDT) 9.8.1 Block Diagram of the WDT Figure 9.4 shows a block diagram of the WDT. Standby Standby cancellation control Internal Reset reset control request Interrupt Interrupt request control WTCSR: Watchdog timer control/status register ...
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WDT Registers 9.9.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT 8-bit read/write counter that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in ...
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Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an interval timer. Bit 6: WT/IT Description 0 Use as interval timer 1 Use as watchdog timer Note: If WT/IT is modified when the ...
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Bit 2: CKS2 Bit 1: CKS1 Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT ...