DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet

IC H8S/2505 MCU FLASH 144QFP

DF2505FC26V

Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2505FC26V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for DF2505FC26V

DF2505FC26V Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2556 Group, 16 H8S/2552 Group, H8S/2506 Group ...

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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...

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This LSI is a high-performance microcomputer made up of the H8S/2000 CPU with an internal 32-bit configuration as its core, and the peripheral functions required to configure a system. A single-power flash memory (F-ZTAT version provides flexibility as it can ...

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Target Users: This manual was written for users who will be using the H8S/2556 Group, H8S/2552 Group, and H8S/2506 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and ...

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H8S/2556, H8S/2552, H8S/2506 manuals: Document Title H8S/2556, H8S/2552, H8S/2506 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.01 User's Manual H8S, ...

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All trademarks and registered trademarks are the property of their respective owners. Rev. 6.00 Sep. 24, 2009 Page viii of xlvi REJ09B0099-0600 ...

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Section 1 Overview..................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram.......................................................................................................... 2 1.3 Pin Arrangements................................................................................................................... 6 1.3.1 Pin Arrangements ..................................................................................................... 6 1.3.2 Pin Arrangements in Each mode............................................................................. 11 1.3.3 Pin Functions .......................................................................................................... 17 Section 2 CPU........................................................................................................25 2.1 Features................................................................................................................................ 25 2.1.1 Differences ...

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Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC) ...................................... 55 2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 55 2.7.9 Effective Address Calculation ................................................................................ 56 2.8 Processing States.................................................................................................................. 59 2.9 Usage Notes ......................................................................................................................... 61 2.9.1 TAS Instruction ...................................................................................................... 61 2.9.2 STM/LDM Instruction............................................................................................ 61 2.9.3 Bit ...

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IRQ Enable Register (IER) ..................................................................................... 90 5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 91 5.3.4 IRQ Status Register (ISR)....................................................................................... 93 5.4 Interrupt Sources.................................................................................................................. 94 5.4.1 External Interrupts .................................................................................................. 94 5.4.2 Internal Interrupts ................................................................................................... 95 ...

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PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction....................................................................................... 121 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ........................................ 121 6.4.7 PC Break Set for Instruction Fetch at ...

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Usage Note for External Bus Mastership Release ................................................ 166 7.11 Resets and the Bus Controller............................................................................................ 166 Section 8 Data Transfer Controller (DTC) ..........................................................167 8.1 Features.............................................................................................................................. 167 8.2 Register Descriptions ......................................................................................................... 169 8.2.1 DTC Mode Register A (MRA) ............................................................................. 170 ...

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Pin Functions ........................................................................................................ 200 9.2 Port 2.................................................................................................................................. 205 9.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 205 9.2.2 Port 2 Data Register (P2DR) ................................................................................ 206 9.2.3 Port 2 Register (PORT2)....................................................................................... 206 9.2.4 Pin Functions ........................................................................................................ 207 9.3 Port 3.................................................................................................................................. 210 ...

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Port B Pull-Up MOS Control Register (PBPCR) ................................................. 234 9.9.5 Pin Functions ........................................................................................................ 235 9.9.6 Input Pull-Up MOS Function (Port B).................................................................. 238 9.10 Port C ................................................................................................................................. 239 9.10.1 Port C Data Direction Register (PCDDR) ............................................................ 239 9.10.2 Port C ...

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Port J Data Direction Register (PJDDR)............................................................... 261 9.16.2 Port J Data Register (PJDR) ................................................................................. 262 9.16.3 Port J Register (PORTJ) ....................................................................................... 262 9.16.4 Pin Functions ........................................................................................................ 263 9.17 Power Supply Pin Control ................................................................................................. 264 9.17.1 IC Power Control Register ...

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Contention between TGR Write and Compare Match .......................................... 346 10.9.7 Contention between Buffer Register Write and Compare Match ......................... 347 10.9.8 Contention between TGR Read and Input Capture............................................... 348 10.9.9 Contention between TGR Write and Input Capture.............................................. 349 10.9.10 ...

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Switching of Internal Clocks and TCNT Operation ............................................. 374 11.8.7 Contention between Interrupts and Module Stop Mode ....................................... 376 11.8.8 Mode Setting in Cascading ................................................................................... 376 Section 12 Watchdog Timer (WDT) ................................................................... 377 12.1 Features.............................................................................................................................. 377 12.2 Input/Output Pin ...

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Data Transfer Format............................................................................................ 425 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 427 13.4.3 Clock..................................................................................................................... 428 13.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 428 13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 430 13.4.6 Serial Data Reception ...

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Section Bus Interface 2 (IIC2).................................................................. 475 14.1 Features.............................................................................................................................. 475 14.2 Input/Output Pins............................................................................................................... 478 14.3 Register Descriptions......................................................................................................... 479 2 14.3 Bus Control Register 1 (ICCR1)..................................................................... 479 2 14.3 Bus Control Register 2 (ICCR2)..................................................................... ...

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A/D Control Register (ADCR) ............................................................................. 520 15.4 Interface to Bus Master ...................................................................................................... 521 15.5 Operation ........................................................................................................................... 522 15.5.1 Single Mode.......................................................................................................... 522 15.5.2 Scan Mode ............................................................................................................ 523 15.5.3 Input Sampling and A/D Conversion Time .......................................................... 524 15.5.4 External Trigger Input ...

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IEBus Master Unit Address Register 2 (IEAR2) .................................................. 564 17.3.6 IEBus Slave Address Setting Register 1 (IESA1)................................................. 564 17.3.7 IEBus Slave Address Setting Register 2 (IESA2)................................................. 565 17.3.8 IEBus Transmit Message Length Register (IETBFL) .......................................... 565 17.3.9 IEBus Transmit ...

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Input/Output Pins ............................................................................................................... 611 18.3 Register Descriptions ......................................................................................................... 611 18.3.1 Master Control Register (MCR) ........................................................................... 612 18.3.2 General Status Register (GSR) ............................................................................. 613 18.3.3 Bit Configuration Register (BCR) ........................................................................ 615 18.3.4 Mailbox Configuration Register (MBCR) ............................................................ 617 18.3.5 Transmit ...

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Usage of Bit Change Instructions ......................................................................... 658 18.8.10 HCAN TXCR Operation ...................................................................................... 658 18.8.11 HCAN Transmit Procedure .................................................................................. 659 18.8.12 Canceling HCAN Software Reset or HCAN Sleep Mode .................................... 661 18.8.13 Accessing Mailboxes in HCAN Sleep Mode........................................................ 661 Section ...

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Auto-Erase Mode.................................................................................................. 738 20.9.6 Status-Read Mode................................................................................................. 739 20.9.7 Status Polling ........................................................................................................ 739 20.9.8 Transition Time to Programmer Mode ................................................................. 740 20.9.9 Notes on Programmer Mode................................................................................. 740 20.10 Serial Communication Interface Specification for Boot Mode.......................................... 741 20.11 AC Characteristics and ...

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Software Standby Mode Application Example..................................................... 802 22.5 Hardware Standby Mode ................................................................................................... 804 22.5.1 Transition to Hardware Standby Mode................................................................. 804 22.5.2 Clearing Hardware Standby Mode........................................................................ 804 22.5.3 Hardware Standby Mode Timing.......................................................................... 804 22.6 Module Stop Mode ............................................................................................................ 805 22.7 Watch ...

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C. Package Dimensions .......................................................................................................... 912 Main Revisions for This Edition..........................................................................915 Index .........................................................................................................923 Rev. 6.00 Sep. 24, 2009 Page xxvii of xlvi REJ09B0099-0600 ...

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Rev. 6.00 Sep. 24, 2009 Page xxviii of xlvi REJ09B0099-0600 ...

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Sction 1 Overview Figure 1.1 Internal Block Diagram of H8S/2556 Group .............................................................. 3 Figure 1.2 Internal Block Diagram of H8S/2552 Group .............................................................. 4 Figure 1.3 Internal Block Diagram of H8S/2506 Group .............................................................. 5 Figure 1.4 Pin Arrangement of H8S/2556 Group ...

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Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 86 Figure 5.2 Block Diagram of IRQ7 to IRQ0 Interrupts.............................................................. 94 Figure 5.3 Set Timing for IRQ7F to IRQ0F ............................................................................... 95 Figure 5.4 Block Diagram of Interrupt Control Operation ...

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Figure 7.25 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 158 Figure 7.26 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 158 Figure 7.27 Example of Idle Cycle Operation (1) ...................................................................... 160 ...

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Figure 10.16 Example of Buffer Operation (2) ............................................................................ 318 Figure 10.17 Cascaded Operation Setting Procedure ................................................................... 319 Figure 10.18 Example of Cascaded Operation (1) ....................................................................... 319 Figure 10.19 Example of Cascaded Operation (2) ....................................................................... 320 Figure 10.20 Example of PWM ...

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Section 11 8-Bit Timers (TMR) Figure 11.1 Block Diagram of 8-Bit Timer Module................................................................... 354 Figure 11.2 Example of Pulse Output......................................................................................... 364 Figure 11.3 Count Timing for Internal Clock Input ................................................................... 365 Figure 11.4 Count Timing for External Clock Input .................................................................. ...

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Figure 13.9 Sample Serial Reception Data Flowchart (2) .......................................................... 435 Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ............................................ 437 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart.......................................... 439 Figure 13.12 Example of ...

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Section Bus Interface 2 (IIC2) Figure 14.1 Block Diagram of I Figure 14.2 External Circuit Connections of I/O Pins................................................................ 478 2 Figure 14 Bus Formats ...................................................................................................... 492 2 Figure 14 Bus Timing........................................................................................................ ...

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Section 17 IEBus™ Controller (IEB) [H8S/2552 Group] Figure 17.1 Block Diagram of IEB ............................................................................................ 540 Figure 17.2 Transfer Signal Format ........................................................................................... 544 Figure 17.3 Bit Configuration of Slave Status (SSR)................................................................. 553 Figure 17.4 Locked Address Configuration ............................................................................... 554 Figure 17.5 ...

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Figure 20.3 Flash Memory Configuration .................................................................................. 671 Figure 20.4 Block Division of User MAT.................................................................................. 672 Figure 20.5 Overview of User Procedure Program .................................................................... 673 Figure 20.6 System Configuration in Boot Mode....................................................................... 699 Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. ...

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Figure 21.3 Crystal Resonator Equivalent Circuit...................................................................... 780 Figure 21.4 External Clock Input (Examples) ............................................................................ 781 Figure 21.5 External Clock Input Timing................................................................................... 782 Figure 21.6 External Clock Switching Circuit (Examples) ........................................................ 783 Figure 21.7 External Clock Switching Timing (Examples)........................................................ 784 Figure ...

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Figure 24.21 SCK Clock Input Timing ........................................................................................ 899 Figure 24.22 SCI Input/Output Timing/Synchronous Mode ........................................................ 899 Figure 24.23 External Trigger Input Timing for A/D Converter.................................................. 900 Figure 24.24 HCAN Input/Output Timing ................................................................................... 900 2 Figure 24. Bus Interface ...

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Rev. 6.00 Sep. 24, 2009 Page xl of xlvi REJ09B0099-0600 ...

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Section 1 Overview Table 1.1 Pin Arrangements in Operating Mode....................................................................... 11 Table 1.2 Pin Functions............................................................................................................. 17 Section 2 CPU Table 2.1 Instruction Classification........................................................................................... 41 Table 2.2 Operation Notation.................................................................................................... 42 Table 2.3 Data Transfer Instructions ......................................................................................... 43 Table 2.4 Arithmetic Operations ...

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Table 5.3 Interrupt Control Modes.......................................................................................... 100 Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1).......................................... 102 Table 5.5 Interrupts Selected in Each Interrupt Control Mode (2).......................................... 102 Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode ...

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Table 10.7 TPSC0 to TPSC2 (channels 2) ................................................................................ 279 Table 10.8 TPSC0 to TPSC2 (channel 3).................................................................................. 279 Table 10.9 TPSC0 to TPSC2 (channel 4).................................................................................. 280 Table 10.10 TPSC0 to TPSC2 (channel 5).................................................................................. 280 Table 10.11 MD0 to MD3........................................................................................................... 282 Table ...

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Section 13 Serial Communication Interface (SCI) Table 13.1 Pin Configuration .................................................................................................... 397 Table 13.2 Relationships between N Setting in BRR and Bit Rate B ....................................... 418 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) ................................... 419 Table 13.4 ...

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Table 17.4 Control Bit Contents................................................................................................ 551 Table 17.5 Control Field for Locked Slave Unit ....................................................................... 552 Table 17.6 Pin Configuration .................................................................................................... 556 Table 17.7 List of System Clock Division Ratio....................................................................... 559 Section 18 Controller Area Network (HCAN) [H8S/2556 Group] Table ...

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Table 20.25 AC Characteristics in Status-Read Mode................................................................ 772 Table 20.26 Transition Time Rules before Command Wait State .............................................. 773 Section 21 Clock Pulse Generator Table 21.1 Damping Resistance Value ..................................................................................... 780 Table 21.2 Crystal Resonator Characteristics ........................................................................... 781 Table 21.3 ...

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Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 65 basic instructions • Various peripheral functions ⎯ PC break ...

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Section 1 Overview • General I/O ports Support two types of the port with different power supply sources ⎯ H8S/2556 Group I/O pins: 102 HCAN pins: 2 (one input and one output) Input pins: 16 ⎯ H8S/2552 Group and H8S/2506 ...

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MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 PLL for STBY system clock RES NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG1/CS3/IRQ7 PG0/IRQ6 P10 / TIOCA0 P11 / TIOCB0 P12 / TIOCC0 / TCLKA P13 / TIOCD0 / ...

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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 PLL for STBY system clock RES NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/Rx/CS1 PG2/Tx/CS2 PG1/CS3/IRQ7 PG0/IRQ6 P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD P27/TIOCB5 P26/TIOCA5 ...

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MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY PLL for system clock RES NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD P27/TIOCB5 P26/TIOCA5 P25/TIOCB4 P24/TIOCA4 P23/TIOCD3 ...

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Section 1 Overview 1.3 Pin Arrangements 1.3.1 Pin Arrangements Figures 1.4 to 1.8 show the pin arrangement. P17/TIOCB2/TCLKD 109 P16/TIOCA2/IRQ1 110 P15/TIOCB1/TCLKC 111 P14/TIOCA1/IRQ0 112 P13/TIOCD0/TCLKB 113 P12/TIOCC0/TCLKA 114 P11/TIOCB0 115 P10/TIOCA0 116 Vss 117 P2Vcc 118 P37/TxD4 119 P36/RxD4 ...

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P17/TIOCB2/TCLKD 109 P16/TIOCA2/IRQ1 110 P15/TIOCB1/TCLKC 111 P14/TIOCA1/IRQ0 112 P13/TIOCD0/TCLKB 113 P12/TIOCC0/TCLKA 114 P11/TIOCB0 115 P10/TIOCA0 116 Vss 117 P2Vcc 118 P37/TxD4 119 P36/RxD4 120 P35/SCK1/SCK4/SCL0/IRQ5 121 P34/RxD1/SDA0 122 P33/TxD1/SCL1 123 P32/SCK0/SDA1/IRQ4 124 P31/RxD0 125 P30/TxD0 126 P77/TxD3 127 P76/RxD3 128 ...

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Section 1 Overview P17/TIOCB2/TCLKD 109 P16/TIOCA2/IRQ1 110 P15/TIOCB1/TCLKC 111 P14/TIOCA1/IRQ0 112 P13/TIOCD0/TCLKB 113 P12/TIOCC0/TCLKA 114 P11/TIOCB0 115 P10/TIOCA0 116 Vss 117 P2Vcc 118 P37/TxD4 119 P36/RxD4 120 P35/SCK1/SCK4/SCL0/IRQ5 121 P34/RxD1/SDA0 122 P33/TxD1/SCL1 123 P32/SCK0/SDA1/IRQ4 124 P31/RxD0 125 P30/TxD0 126 P77/TxD3 ...

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P17/ P26/ P23/ P20/ 15 TIOCB2/ TIOCA5 TIOCD3 TIOCA3 TCLKD P27/ P25/ P21/ 14 Vss TIOCB5 TIOCB4 TIOCB3 P15/ P16/ P22/ 13 Vss TIOCB1/ TIOCA2/ TIOCC3 IRQ1 TCLKC P13/ P14/ P24/ 12 Vss TIOCD0/ TIOCA1/ TIOCA4 ...

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Section 1 Overview P17/ P26/ P23/ P20/ 15 TIOCB2/ TIOCA5 TIOCD3 TIOCA3 TCLKD P27/ P25/ P21/ 14 Vss TIOCB5 TIOCB4 TIOCB3 P15/ P16/ P22/ 13 Vss TIOCB1/ TIOCA2/ TIOCC3 IRQ1 TCLKC P13/ P14/ P24/ 12 Vss ...

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Pin Arrangements in Each mode Pin arrangements in each mode are shown below. Table 1.1 Pin Arrangements in Operating Mode Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode PE5/ PE6/ PE7/D7 ...

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Section 1 Overview Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode PC6/ PC7/ PB0/ PB1/ PB2/A10 25 L3 PB3/A11 26 L1 PB4/A12 27 L2 PB5/A13 28 L4 PB6/A14 ...

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Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode PJ5 49 M6 PJ4 50 N6 PJ3 51 P6 PJ2 52 M7 PJ1 53 N7 PJ0 54 R7, R6, Vss P8 P97/AN15/DA1 56 N8 P96/AN14/DA0 ...

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Section 1 Overview Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode 6 75 N14 P51/RxD2 76 M13 P52/SCK2 77 N15 PF0/BREQ/IRQ2 78 M14 PF1/BACK/BUZZ 79 L12 PF2/WAIT 80 M15 PF3/LWR/ADTRG/ IRQ3 HWR 81 L13 RD 82 L14 AS 83 ...

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Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode 6 101 D15 P20/TIOCA3 102 D14 P21/TIOCB3 103 D13 P22/TIOCC3 104 C15 P23/TIOCD3 105 D12 P24/TIOCA4 106 C14 P25/TIOCB4 107 B15 P26/TIOCA5 108 B14 P27/TIOCB5 109 A15 P17/TIOCB2/ TCLKD 110 C13 ...

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Section 1 Overview Pin No. Pin Name FP-144J, 4 FP-144JV BP-176V* Mode 6 125 D7 P31/RxD0 126 C7 P30/TxD0 127 A7 P77/TxD3 128 B7 P76/RxD3 129 D6 P75/TMO3/SCK3 130 C6 P74/TMO2/MRES P74/TMO2/MRES 131 A6 P73/TMO1/CS7 132 B6 P72/TMO0/CS6 133 C5 ...

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Pin Functions Table 1.2 lists the pins functions in each mode. Table 1.2 Pin Functions Pin No. FP-144J, Type Symbol FP-144JV BP-176V* Power Vcc 96 supply P1Vcc 14, 84 P2Vcc 118 VCL 88 VSS 12, 54, 86, 94, 117 ...

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Section 1 Overview Pin No. FP-144J, Type Symbol FP-144JV BP-176V* Clock OSC1 90 OSC2 89 φ 85 Operating MD2 92 mode MD1 98 control MD0 97 RES* 1 System 100 control MRES* 1 130 STBY BREQ 77 BACK ...

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Pin No. FP-144J, Type Symbol FP-144JV BP-176V* Address A23 15, bus 13 Data bus D15 144 to 140 CS7 Bus 131 control CS6 132 CS5 133 CS4 134 CS3 138 CS2 ...

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Section 1 Overview Pin No. FP-144J, Type Symbol FP-144JV BP-176V* WAIT Bus 79 control 16-bit TCLKD 109 timer- TCLKC 111 pulse unit TCLKB 113 (TPU) TCLKA 114 TIOCA0 116 TIOCB0 115 TIOCC0 114 TIOCD0 113 TIOCA1 112 TIOCB1 111 TIOCA2 ...

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Pin No. FP-144J, Type Symbol FP-144JV BP-176V* Watch BUZZ 78 dog timer (WDT) Serial TxD4 119 communi- TxD3 127 cation TxD2 74 interface (SCI)/ TxD1 123 smart TxD0 126 card RxD4 120 interface RxD3 128 RxD2 75 RxD1 122 RxD0 ...

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Section 1 Overview Pin No. FP-144J, Type Symbol FP-144JV BP-176V* A/D AVcc 73 converter, D/A converter AVss 67 Vref IEBus 137 controller (IEB) Rx 136 Controller HTxD 137 area network HRxD 136 (HCAN) I/O ports P17 to ...

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Pin No. FP-144J, Type Symbol FP-144JV BP-176V* I/O ports P77 to 127 to P70 134 P97 P90 PA7 PA0 PB7 PB0 PC7 15, PC0 13 ...

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Section 1 Overview Pin No. FP-144J, Type Symbol FP-144JV BP-176V* I/O ports PH7 PH0 PJ7 PJ0 Notes: 1. Countermeasure against noise should be executed or may result in malfunction. 2. Available only ...

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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...

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Section 2 CPU ⎯ 16 × 16-bit register-register multiply : 20 states ⎯ 32 ÷ 16-bit register-register divide • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by a SLEEP ...

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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been ...

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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...

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Note: * Normal mode is not available in this LSI. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is ...

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Section 2 CPU The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used. • Exception ...

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Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they ...

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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...

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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended control register (EXR), ...

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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...

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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...

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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...

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Bit Bit Name Initial Value 2 Z Undefined 1 V Undefined 0 C Undefined 2.4.5 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to ...

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Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...

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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn : General register General register General register R RnH : General register RH RnL ...

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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...

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Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* , STM* MOVFPE* Arithmetic ADD, SUB, CMP, NEG operations ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* ...

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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General ...

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Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), and 32-bit registers (ER0 ...

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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L Performs addition or subtraction on data in two general registers SUB immediate data and ...

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Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 ...

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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...

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Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...

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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result ...

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Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...

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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC ...

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Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...

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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing ...

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Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 2.7.1 Register ...

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Section 2 CPU longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement⎯@-ERn: The value subtracted from an address register (ERn) specified by the register ...

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The ADDS, SUBS, INC and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a ...

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Section 2 CPU Specified by @aa:8 (a) Normal Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated ...

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Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Register direct(Rn) Register indirect(@ERn) Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ •Register indirect with pre-decrement @-ERn Effective Address Calculation General register contents General register contents ...

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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Rev. 6.00 Sep. 24, 2009 Page 58 of 928 REJ09B0099-0600 Effective Address Calculation ...

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Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and ...

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Section 2 CPU Bus-released state Exception handling state MRES = high Manual reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition ...

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Usage Notes 2.9.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the H8S and H8/300 Series C/C++ compilers. If the TAS instruction is ...

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Section 2 CPU The BSET, BCLR, BNOT, BST and BIST instructions are executed as follows: 1. Data is read in bytes. 2. The operation corresponding to the instruction is applied to the specified bit of the data. 3. The byte ...

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The target bit of the data read out is then manipulated. In this example, clearing bit 4 of H'F8 leaves us with H'E8. P17 I/O Output Output P1DDR 1 After bit- 1 manipulation After the bit-manipulation, The data is then ...

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Section 2 CPU Write initial data to work area Copy data from work area to register including write-only bit Access data in work area (data-transfer and bit-manipulation instructions can be used) Copy data from work area to register including write-only ...

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P17 P16 I/O Output Output P1DDR 1 RAM0 1 RAM locations are readable and writable, so there is no possibility of a problem if a bit- manipulation instruction is used to clear only bit 4 of RAM0. Read the value ...

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Section 2 CPU Rev. 6.00 Sep. 24, 2009 Page 66 of 928 REJ09B0099-0600 ...

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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports two types of operating mode (modes 6 and 7). Pin functions are changed according to each operating mode. The operation mode is determined by the setting of mode ...

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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode. Initial Bit ...

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Initial Bit Bit Name Value ⎯ ⎯ INTM1 0 4 INTM0 0 3 NMIEG 0 2 MRESE 0 ⎯ RAME 1 R/W Descriptions R/W Reserved The write value should always be 0. ...

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Section 3 MCU Operating Modes 3.3 Operating Mode 3.3.1 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is valid. Immediately after a reset, ports A, B, and C become input ports. The ...

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Table 3.2 Pin Function in Each Operating Mode Port Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Legend: P: Input/output port A: Address bus output D: Data bus ...

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Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 to 3.3 show the address map of each product. Mode 6 (Advanced and expanded mode with on-chip ROM enabled) H'000000 H'080000 H'FF7000 H'FFEFC0 External address space ...

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Mode 6 (Advanced and expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'060000 Reserved area H'080000 External address space H'FF7000 Reserved area H'FF9000 On-chip RAM H'FFEFC0 External address space H'FFF800 Internal I/O registers H'FFFF40 Reserved area H'FFFF60 Internal I/O ...

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Section 3 MCU Operating Modes Mode 6 (Advanced and expanded mode with on-chip ROM enabled) H'000000 H'060000 H'080000 H'FF7000 H'FFEFC0 External address space H'FFF800 Internal I/O registers H'FFFF40 H'FFFF60 Internal I/O registers H'FFFFC0 H'FFFFFF Rev. 6.00 Sep. 24, 2009 Page ...

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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more ...

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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace 3 Direct transitions* External interrupt (NMI) Trap instruction (four sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 ...

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Reset A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and this LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of ...

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Section 4 Exception Handling 4.3.2 Reset Exception Handling When the RES or MRES pin goes low, this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least ...

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Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...

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Section 4 Exception Handling Table 4.4 State of CCR and EXR after Trace Exception Handling Interrupt Control Mode 0 2 Legend: 1: Set Cleared to 0 ⎯: Retains value prior to execution 4.5 Interrupt Exception Handling Interrupts ...

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The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from specified in the instruction code. Table 4.5 shows the state of CCR and EXR after execution of trap ...

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Section 4 Exception Handling 4.7 Stack State after Exception Handling Figures 4.2 shows the stack state after completion of trap instruction exception handling and interrupt exception handling. SP (a) Interrupt control mode 0 Note:* Ignored on return. Figure 4.2 Stack ...

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SP SP TRAPA instruction executed SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in interrupt control mode 0 and advanced mode. Figure 4.3 ...

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Section 4 Exception Handling Rev. 6.00 Sep. 24, 2009 Page 84 of 928 REJ09B0099-0600 ...

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Section 5 Interrupt Controller 5.1 Features This LSI controls interrupts with the interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the ...

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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input Internal interrupt source SWDTEND to TEI4 Interrupt controller Legend: IRQ sense control register ISCR: IRQ enable ...

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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising edge or falling edge can be selected. IRQ7 Input Maskable external interrupt IRQ6 Input Rising ...

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Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). • System control register (SYSCR) • IRQ sense control register H (ISCRH) ...

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Interrupt Priority Registers and O (IPRA to IPRM, IPRO) The IPR registers are fourteen 8-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR ...

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Section 5 Interrupt Controller 5.3.2 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Initial Bit Bit Name Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E ...

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IRQ Sense Control Registers H and L (ISCRH and ISCRL) The ISCR registers select the source that generates an interrupt request at IRQ7 to IRQ0 pins. Specifiable sources are the falling edge, rising edge, both edges, and level sensing. ...

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Section 5 Interrupt Controller Initial Bit Bit Name Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 Rev. 6.00 Sep. 24, 2009 Page 92 of 928 REJ09B0099-0600 R/W Description R/W ...

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Initial Bit Bit Name Value 1 IRQ0SCB 0 0 IRQ0SCA 0 5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQ7 to IRQ 0 interrupt requests. Initial Bit Bit Name Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F ...

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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are 9 external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, ...

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IRQn input pin IRQnF Note Figure 5.3 Set Timing for IRQ7F to IRQ0F The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. ...

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Section 5 Interrupt Controller Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Interrupt Source External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTC SWDTEND (completion of software initiation data transfer) Watchdog WOVI0 ...

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Origin of Interrupt Source Interrupt Source TPU channel TGI0D (TGR0D input 0 capture/compare- match) TCI0V (overflow 0) ⎯ Reserved TPU channel TGI1A (TGR1A input 1 capture/compare-match) TGI1B (TGR1B input capture/compare-match) TCI1V (overflow 1) TCI1U (underflow 1) TPU channel TGI2A (TGR2A ...

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Section 5 Interrupt Controller Origin of Interrupt Source Interrupt Source TPU channel TGI4A (TGR4A input 4 capture/compare-match) TGI4B (TGR4B input capture/compare-match) TCI4V (overflow 4) TCI4U (underflow 4) TPU channel TGI5A (TGR5A input 5 capture/compare-match) TGI5B (TGR5B input capture/compare-match) TCI5V (overflow ...

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Origin of Interrupt Source Interrupt Source SCI channel 2 TXI2 (transmit data empty 2) 90 TEI2 (transmit end 2) 8-bit timer CMIA2 (compare-match A2) 92 channel 2 CMIB2 (compare-match B2) 93 OVI2 (overflow 2) ⎯ Reserved 8-bit timer CMIA3 (compare-match ...

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Section 5 Interrupt Controller 5.5 Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware ...

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Interrupt control mode 0 Interrupt acceptance control Interrupt source 8-level mask control IPR Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation I Default priority determination Rev. 6.00 Sep. 24, 2009 Page 101 of ...

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Section 5 Interrupt Controller Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.4 shows the interrupts selected in each interrupt control mode. Table 5.4 Interrupts Selected in Each Interrupt ...

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Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Setting Control Interrupt Control INTM INTM Mode Legend Interrupt operation control performed X: No ...

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Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address. IRQ0 Yes Figure 5.5 Flowchart of ...

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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip peripheral module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...

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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance Rev. 6.00 Sep. 24, 2009 Page 106 of 928 REJ09B0099-0600 Program execution status No Interrupt generated? Yes ...

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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...

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Section 5 Interrupt Controller Figure 5.7 Interrupt Exception Handling Rev. 6.00 Sep. 24, 2009 Page 108 of 928 REJ09B0099-0600 ...

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Interrupt Response Times This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.7 shows interrupt response times — the ...

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Section 5 Interrupt Controller Table 5.8 Number of States in Interrupt Handling Routine Execution Status Symbol Instruction fetch S Branch address read S Stack manipulation S Legend: m: Number of wait states in an external device access. Note: * Not ...

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Interrupt request IRQ interrupt Interrupt source clear signal On-chip peripheral module Interrupt controller Figure 5.8 DTC and Interrupt Controller Interrupt controller of DTC control has the following three main functions. Interrupt Source Selection: For interruption source, select DTC activation request ...

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Section 5 Interrupt Controller Operation Order: When the same interrupts are selected as DTC activation source and CPU interruption source, DTC data is transferred, and then CPU interrupt exception processing is made. Table 5.9 shows interrupt source selection and interrupt ...

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The same also applies when an interrupt source flag is cleared to 0. The above contention will not occur enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Figure 5.9 shows an ...

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Section 5 Interrupt Controller The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.6.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs ...

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Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an ...

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Section 6 PC Break Controller (PBC) BARA Comparator Internal address Access status Comparator BARB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. • Break address register A (BARA) • ...

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Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. Initial Bit Bit Name Value ...

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Section 6 PC Break Controller (PBC) Initial Bit Bit Name Value 0 BIEA 0 Notes: 1. Only 0 can be written to this bit to clear the flag. 2. Read the state wherein CMFA = 1 twice or more, when ...

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PC Break Interrupt Due to Data Access 1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack ...

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Section 6 PC Break Controller (PBC) • When the SLEEP instruction causes a transition to software standby mode or watch mode After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break exception handling ...

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Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. ...

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Section 6 PC Break Controller (PBC) 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, and ...

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This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. As the bus controller has a bus mastership arbitration function, it controls the operation of the CPU (the internal bus master) and ...

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Section 7 Bus Controller Figure 7.1 shows a block diagram of the bus controller. Chip select signal External bus control signal BREQ BACK WAIT Legend: ABWCR: Bus width control register ASTCR: Access state control register WCRH, WCRL: Wait control registers ...

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Input/Output Pins Table 7.1 summarizes the pins of the bus controller. Table 7.1 Pin Configuration Name Symbol AS Address strove RD Read HWR High write LWR Low write Chip select CS0 to CS7* WAIT Wait BREQ ...

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Section 7 Bus Controller 7.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area as either an 8-bit access space or a 16-bit access space. ABWCR sets the data bus width for the external memory space. The bus width for ...

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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program wait states are not inserted in the case of on-chip memory or internal I/O registers. • WCRH ...

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Section 7 Bus Controller Initial Bit Bit Name Value 1 W41 1 0 W40 1 • WCRL Initial Bit Bit Name Value 7 W31 1 6 W30 1 5 W21 1 4 W20 1 Rev. 6.00 Sep. 24, 2009 Page ...

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Initial Bit Bit Name Value 3 W11 1 2 W10 1 1 W01 1 0 W00 1 R/W Description R/W Area 1 Wait Control 1 and 0 R/W These bits select the number of program wait states when area 1 ...

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Section 7 Bus Controller 7.3.4 Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. Initial Bit Bit Name Value 7 ICIS1 1 6 ICIS0 1 5 BRSTRM 0 ...

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Initial Bit Bit Name Value ⎯ All 0 7.3.5 Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of the WAIT pin input. Initial Bit Bit Name Value ...

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Section 7 Bus Controller 7.3.6 Pin Function Control Register (PFCR) PFCR performs address output control in external extended mode. Initial Bit Bit Name Value ⎯ All 0 5 BUZZE 0 ⎯ Rev. 6.00 Sep. 24, 2009 ...

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Initial Bit Bit Name Value R/W 3 AE3 0 R/W 2 AE2 0 R/W 1 AE1 0 R/W 0 AE0 0 R/W Description Address Output Enable These bits select enabling or disabling of address outputs A8 to ...

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Section 7 Bus Controller 7.4 Bus Control 7.4.1 Area Divisions In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, area 0 to area 7, in 2-Mbyte units, and performs bus control for external address space ...

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H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FFFFFF Note: * Not available in this LSI. Figure 7.2 Overview of Area Divisions 7.4.2 Bus Specifications The external address space bus specifications consist of ...

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Section 7 Bus Controller If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16- bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus ...

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Area 0: Area 0 includes on-chip ROM, and in ROM-enabled extended mode, space excluding on- chip ROM is external address space. When external address space of area 0 is accessed, the CS0 signal can be output. Either basic bus interface ...

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Section 7 Bus Controller φ Address bus CSn Figure 7.3 CSn Signal Output Timing ( Rev. 6.00 Sep. 24, 2009 Page 138 of 928 REJ09B0099-0600 Bus cycle External address of ...

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Basic Timing The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred "state." The memory cycle or bus cycle consists ...

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Section 7 Bus Controller Address bus AS RD HWR, LWR Data bus Figure 7.5 Pin States during On-Chip Memory Access 7.5.2 On-Chip Peripheral Module Access Timing On-Chip Peripheral Module Access Timing Excluding Port H, Port J, IIC2, IEB, and HCAN: ...

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Address bus AS RD HWR, LWR Data bus Figure 7.7 Pin States during On-Chip Peripheral Module Access On-Chip Port H, Port J, and IIC2 Module Access Timing: On-chip port H, port J, and IIC2 modules are accessed in four states. ...

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Section 7 Bus Controller φ Address bus AS RD HWR, LWR Data bus Figure 7.9 Pin States during On-Chip Port H, Port J, and IIC2 Module Access On-Chip IEB Module Access Timing (H8S/2552 Group Only): On-chip IEB module is accessed ...

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Address bus AS RD HWR, LWR Data bus Figure 7.11 Pin States during On-Chip IEB Module Access On-Chip HCAN Module Access Timing (H8S/2556 Group Only):On-chip HCAN module is accessed in five states. At this time, the data bus width ...

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Section 7 Bus Controller φ Address bus AS RD HWR, LWR Data bus Figure 7.13 Pin States during On-Chip HCAN Module Access 7.5.3 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data ...

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Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 7.6.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus ...

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Section 7 Bus Controller Byte size Byte size Word size Longword size Figure 7.15 Access Sizes and Data Alignment Control (16-Bit Access Space) 7.6.2 Valid Strobes Table 7.3 shows the data buses used and valid strobes for the access spaces. ...

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Basic Timing 8-Bit 2-State Access Space: Figure 7.16 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states ...

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Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7.17 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait ...

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Access Space: Figures 7.18 to 7.20 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for an even address, ...

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Section 7 Bus Controller Address bus D15 to D8 Read Write D15 to D8 Note Figure 7.19 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 6.00 Sep. 24, 2009 Page ...

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Address bus CSn AS RD D15 to D8 Read HWR LWR Write D15 Note Figure 7.20 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) ...

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Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7.21 to 7.23 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used ...

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