HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet
HD6417705F133BV
Specifications of HD6417705F133BV
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HD6417705F133BV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7705 Group 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH7700 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7705 Group Hardware Manual REJ09B0082-0200O ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules CPU and System-Control Modules On-Chip Peripheral Modules ...
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The SH7705 single-chip RISC (Reduced Instruction Set Computer) microprocessor includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target users: This manual was written for users who will be using ...
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Rules: Register name: Bit order: Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions ...
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Abbreviations ADC Analog to Digital Converter ALU Arithmetic Logic Unit ASE Adaptive System Evaluator ASID Address Space Identifier AUD Advanced User Debugger BCD Binary Coded Decimal bps bit per second BSC Bus State Controller CCN Cache Memory Controller CMT Compare ...
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SDRAM Synchronous DRAM TAP Test Access Port T.B Determined TLB Translation Lookaside Buffer TMU Timer Unit TPU Timer Pulse Unit UART Universal Asynchronous Receiver/Transmitter UBC User Break Controller USB Universal Serial Bus WDT Watchdog Timer Rev. 2.00, 09/03, ...
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Main Revisions and Additions in this Edition Item 1.1 SH7705 Features Table 1.1 SH7705 Features 1.3 Pin Assignment Table 1.2 Pin Functions 4.4.1 Address Array Address-Array Write (Associative Operation) 4.4.3 Usage Examples Invalidating a Specific Entry Invalidating an Address Specification ...
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Item 6.1 Features Figure 6.1 Block Diagram of INTC 6.4.6 Interrupt Exception Handling and Priority Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) 7.4.2 CSn Space Bus Control Register (CSnBCR 5A, 5B, ...
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Item 7.13 Others Reset 8.3.4 DMA Channel Control Registers (CHCR) 8.4.3 Channel Priority Round-Robin Mode 8.4.4 DMA Transfer Types Address Modes Figure 8.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) Bus Mode and ...
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Item 9.1 Features Figure 9.1 Block Diagram of Clock Pulse Generator 10.2.2 Watchdog Timer Control/Status Register (WTCSR) 11.6.1 Transition to Module Standby Function 16.5 SCIF Interrupt Sources and DMAC Table 16.4 SCIF Interrupt Sources 18.1 Features 19.2.7 Port F Control ...
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Item 22.2.10 Execution Times Break Register (BETR) 23.2 Input/Output Pins 23.3.3 Boundary Scan Register (SDBSR) 23.5.2 Points for Attention 24.1 Register Addresses (by functional module, in order of the corresponding section numbers) Page Revisions (See Manual for Details) 552 Note ...
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Item 25.3.1 Clock Timing Figure 25.5 Power-On Oscillation Settling Time 25.3.2 Control Signal Timing Table 25.6 Control Signal Timing Figure 25.15 Pin Drive Timing at Standby 25.3.4 Basic Timing Figure 25.16 Basic Bus Cycle (No Wait) Figure 25.17 Basic Bus ...
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Item 25.3.4 Basic Timing Figure 25.18 Basic Bus Cycle (One External Wait) Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM Bit = 0), No Idle Cycle Setting) 25.3.11 SCIF Module Signal Timing Table 25.13 SCIF Module ...
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Item A. I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State Rev. 2.00, 09/03, page xviii of xlvi Page Revisions (See Manual for Details) 682, Note *13 added 684 Reset Power- on Category ...
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Section 1 Overview ....................................................................................... 1 1.1 SH7705 Features.......................................................................................................... 1 1.2 Block Diagram............................................................................................................. 6 1.3 Pin Assignment............................................................................................................ 7 1.4 Pin Functions............................................................................................................... 17 Section 2 CPU ............................................................................................... 25 2.1 Processing States and Processing Modes....................................................................... 25 2.1.1 Processing States ............................................................................................. 25 2.1.2 Processing ...
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TLB Indexing.................................................................................................. 77 3.3.3 TLB Address Comparison ............................................................................... 78 3.3.4 Page Management Information ........................................................................ 80 3.4 MMU Functions .......................................................................................................... 81 3.4.1 MMU Hardware Management ......................................................................... 81 3.4.2 MMU Software Management .......................................................................... 81 3.4.3 MMU Instruction (LDTLB)............................................................................. 82 3.4.4 Avoiding ...
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Interrupt Event Register (INTEVT).................................................................. 111 5.1.4 Interrupt Event Register 2 (INTEVT2)............................................................. 112 5.1.5 Exception Address Register (TEA) .................................................................. 112 5.2 Exception Handling Function ....................................................................................... 113 5.2.1 Exception Handling Flow ................................................................................ 113 5.2.2 Exception Vector Addresses ............................................................................ 114 5.2.3 Exception ...
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Pin Configuration ........................................................................................................ 151 7.3 Area Overview............................................................................................................. 152 7.3.1 Address Map................................................................................................... 152 7.3.2 Memory Bus Width ......................................................................................... 154 7.3.3 Shadow Space ................................................................................................. 155 7.4 Register Descriptions................................................................................................... 155 7.4.1 Common Control Register (CMNCR).............................................................. 156 7.4.2 CSn Space Bus Control Register ...
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DMA Transfer Count Registers (DMATCR).................................................... 243 8.3.4 DMA Channel Control Registers (CHCR)........................................................ 243 8.3.5 DMA Operation Register (DMAOR) ............................................................... 248 8.3.6 DMA Extended Resource Selectors 0, 1 (DMARS0, DMARS1)....................... 250 8.4 Operation..................................................................................................................... 252 8.4.1 Transfer Flow.................................................................................................. 252 8.4.2 DMA ...
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Register Descriptions................................................................................................... 295 11.3.1 Standby Control Register (STBCR) ................................................................. 296 11.3.2 Standby Control Register 2 (STBCR2)............................................................. 297 11.3.3 Standby Control Register 3 (STBCR3)............................................................. 298 11.4 Sleep Mode.................................................................................................................. 299 11.4.1 Transition to Sleep Mode................................................................................. 299 11.4.2 Canceling Sleep Mode..................................................................................... 299 ...
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Compare Match Counter (CMCNT)................................................................. 326 13.2.4 Compare Match Constant Register (CMCOR).................................................. 326 13.3 Operation..................................................................................................................... 326 13.3.1 Period Count Operation ................................................................................... 326 13.3.2 CMCNT Count Timing.................................................................................... 327 13.3.3 Compare Match Flag Set Timing ..................................................................... 327 Section 14 16-Bit Timer Pulse ...
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Year Alarm Register (RYRAR) ....................................................................... 364 15.3.16 RTC Control Register 1 (RCR1) ...................................................................... 365 15.3.17 RTC Control Register 2 (RCR2) ...................................................................... 366 15.3.18 RTC Control Register 3 (RCR3) ...................................................................... 368 15.4 Operation .................................................................................................................... 369 15.4.1 Initial Settings of Registers ...
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Register Description..................................................................................................... 432 17.3.1 IrDA Mode Register (SCSMR_Ir).................................................................... 432 17.4 Operation..................................................................................................................... 434 17.4.1 Overview......................................................................................................... 434 17.4.2 Transmitting.................................................................................................... 434 17.4.3 Receiving ........................................................................................................ 435 17.4.4 Data Format Specification ............................................................................... 435 Section 18 USB Function Module.................................................................. 437 18.1 Features ....................................................................................................................... 437 18.2 ...
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Forcible Stall by Application ........................................................................... 465 18.6.3 Automatic Stall by USB Function Module ....................................................... 467 18.7 DMA Transfer ............................................................................................................. 468 18.7.1 Overview ........................................................................................................ 468 18.7.2 DMA Transfer for Endpoint 1.......................................................................... 468 18.7.3 DMA Transfer for Endpoint 2.......................................................................... 469 18.8 ...
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Port C .......................................................................................................................... 510 20.3.1 Register Description ........................................................................................ 510 20.3.2 Port C Data Register (PCDR)........................................................................... 510 20.4 Port D.......................................................................................................................... 511 20.4.1 Register Description ........................................................................................ 511 20.4.2 Port D Data Register (PDDR) .......................................................................... 511 20.5 Port E .......................................................................................................................... 513 20.5.1 ...
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Operation .................................................................................................................... 533 21.4.1 Single Mode.................................................................................................... 533 21.4.2 Multi Mode ..................................................................................................... 533 21.4.3 Scan Mode ...................................................................................................... 534 21.4.4 Input Sampling and A/D Conversion Time....................................................... 534 21.5 Interrupts and DMAC Transfer Request ....................................................................... 536 21.6 Definitions of A/D Conversion Accuracy ...
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Input/Output Pins......................................................................................................... 568 23.3 Register Descriptions ................................................................................................... 569 23.3.1 Bypass Register (SDBPR)................................................................................ 569 23.3.2 Instruction Register (SDIR) ............................................................................. 569 23.3.3 Boundary Scan Register (SDBSR) ................................................................... 570 23.3.4 ID Register (SDID).......................................................................................... 577 23.4 Operation..................................................................................................................... 578 23.4.1 TAP Controller................................................................................................ 578 23.4.2 ...
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AC Characteristics Measurement Conditions ................................................... 677 25.4 A/D Converter Characteristics...................................................................................... 678 Appendix .....................................................................................................679 A. I/O Port States in Each Processing State ....................................................................... 679 B. Package Dimensions .................................................................................................... 685 Index .....................................................................................................687 Rev. 2.00, 09/03, page xxxii of xlvi ...
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Section 1 Overview Figure 1.1 Block Diagram of SH7705 ........................................................................................6 Figure 1.2 Pin Assignment (FP-208C) .......................................................................................7 Figure 1.3 Pin Assignment (TBP-208A).....................................................................................8 Section 2 CPU Figure 2.1 Processing State Transitions.................................................................................... 26 Figure 2.2 Logical Address to External Memory Space Mapping ............................................. ...
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Figure 6.2 Example of IRL Interrupt Connection ................................................................... 137 Figure 6.3 Interrupt Operation Flowchart............................................................................... 146 Section 7 Bus State Controller (BSC) Figure 7.1 BSC Functional Block Diagram ............................................................................ 150 Figure 7.2 Address Space ...................................................................................................... 154 Figure 7.3 Continuous Access for ...
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Section 8 Direct Memory Access Controller (DMAC) Figure 8.1 Block Diagram of DMAC ..................................................................................... 240 Figure 8.2 DMAC Transfer Flowchart ................................................................................... 253 Figure 8.3 Round-Robin Mode .............................................................................................. 258 Figure 8.4 Channel Priority in Round-Robin Mode ................................................................ 259 Figure 8.5 Data ...
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Figure 11.10 Hardware Standby Mode (When CA Goes Low in Normal Operation)............... 307 Figure 11.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation while Standby Mode Is Canceled) ............................................ 307 Section 12 Timer Unit (TMU) Figure 12.1 ...
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Figure 16.2 Sample SCIF Initialization Flowchart .................................................................. 406 Figure 16.3 Sample Serial Transmission Flowchart ................................................................ 407 Figure 16.4 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 409 Figure 16.5 Example of Transmit Data Stop Function ...
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Figure 18.12 Operation of EP3 Interrupt-In Transfer.............................................................. 463 Figure 18.13 Forcible Stall by Application............................................................................. 466 Figure 18.14 Automatic Stall by USB Function Module......................................................... 467 Figure 18.15 RDFN Bit Operation for EP1 ............................................................................ 468 Figure 18.16 PKTE Bit Operation for EP2............................................................................. ...
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Figure 25.3 CKIO Clock Input Timing .................................................................................. 632 Figure 25.4 CKIO Clock Output Timing ................................................................................ 632 Figure 25.5 Power-On Oscillation Settling Time .................................................................... 633 Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) ............................ 633 Figure 25.7 Oscillation ...
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Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read 4) (Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2, TRCD = 1 Cycle) ................................................................. 655 Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read 4) ...
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Appendix Figure B.1 Package Dimensions (FP-208C) ........................................................................... 685 Figure B.2 Package Dimensions (TBP-208A) ........................................................................ 686 Rev. 2.00, 09/03, page xli of xlvi ...
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Section 1 Overview Table 1.1 SH7705 Features...................................................................................................... 2 Table 1.2 Pin Functions ........................................................................................................... 9 Table 1.3 Pin Functions ......................................................................................................... 17 Section 2 CPU Table 2.1 Logical Address Space ........................................................................................... 28 Table 2.2 Register Initial Values ............................................................................................ 30 Table 2.3 Addressing ...
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Section 7 Bus State Controller (BSC) Table 7.1 Pin Configuration ................................................................................................. 151 Table 7.2 Physical Address Space Map ................................................................................ 152 Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size .......... 154 Table 7.4 32-Bit External Device/Big Endian ...
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Table 11.2 Pin Configuration ............................................................................................. 295 Section 12 Timer Unit (TMU) Table 12.1 Pin Configuration ............................................................................................. 311 Table 12.2 TMU Interrupt Sources..................................................................................... 322 Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.1 TPU Functions ................................................................................................. 330 Table 14.2 Pin Configuration ...
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Table 20.10 Port K Data Register (PKDR) Read/Write Operations ....................................... 520 Table 20.11 Port L Data Register (PLDR) Read/Write Operation ......................................... 521 Table 20.12 Port M Data Register (PMDR) Read/Write Operations...................................... 522 Table 20.13 Port N Data Register (PNDR) Read/Write ...
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Appendix Table A.1 I/O Port States in Each Processing State............................................................ 679 Rev. 2.00, 09/03, page xlvi of xlvi ...
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SH7705 Features This LSI is a microprocessor that integrates a 32-bit RISC-type SuperH architecture CPU as its core, together with 32-kbyte cache memory as well as peripheral functions required for system configuration such as an interrupt controller. High-speed data ...
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Table 1.1 SH7705 Features Item Features CPU Original Renesas SuperH architecture Compatible with SH-1, SH-2 and SH-3 at object code level 32-bit internal data bus General-registers Sixteen 32-bit general registers (eight 32-bit shadow registers) Five 32-bit control registers Four 32-bit ...
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Item Features Bus state Physical address space is divided into eight areas: area 0, areas controller (BSC) each a maximum of 64 Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum of 32 Mbytes The following ...
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Item Features Timer unit (TMU) Three-channel auto-reload-type 32-bit timer Input capture function (only channel 2) Five types of counter input clocks can be selected (P /4, P /16, P /64, P /256, TCLK input) Compare match 16-bit counter timer (CMT) ...
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Item Features User debugging Supports the E10A emulator interface (UDI) JTAG-standard pin assignment Real-time branch trace (AUD) Power-supply I/O: 3.3 voltage Product lineup Power Supply Voltage Product Name I/O SH7705 3.3 0.3 V, internal: 1.5 0.1 V On-chip Operating Modules ...
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Block Diagram Figure 1.1 shows an internal block diagram of the SH7705. CCN CACHE MMU TLB INTC CPG/WDT External bus interface Legend: CACHE: Cache memory CCN: Cache memory controller MMU: Memory management unit TLB: Translation look-aside buffer INTC: Interrupt ...
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Pin Assignment STATUS0/PTE4/RTS0 157 STATUS1/PTE5/CTS0 158 V Q 159 SS CKIO 160 V Q 161 CC PTN0/SUSPND 162 PTN1/TXENL 163 PTN2/XVDATA 164 PTN3/TXDMNS 165 PTN4/TXDPLS 166 PTN5/DMNS 167 PTN6/DPLS 168 PTN7 169 TCLK/PTE6 170 PTE7 171 TxD0/SCPT0/IrTX 172 SCK0/SCPT1 ...
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Note: The terminal area surrounded by the dotted line is the perspective view. Figure 1.3 ...
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Table 1.2 Pin Functions Pin No. FP- TBP- 208C 208A Pin Name 1 A1 VssQ 2 B1 Vcc-USB Vss-USB 5 Vcc-RTC * XTAL2 8 D1 EXTAL2 5 Vss-RTC ...
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Pin No. FP- TBP- 208C 208A Pin Name 32 K4 VssQ 33 L1 D15 34 L2 VccQ 35 L3 D14 36 L4 D13 37 M1 D12 38 M2 D11 39 M3 D10 ...
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Pin No. FP- TBP- 208C 208A Pin Name A10 66 R6 A11 67 T6 A12 68 U6 A13 69 P7 VssQ 70 R7 A14 71 T7 VccQ 72 U7 A15 73 P8 A16 74 R8 ...
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Pin No. FP- TBP- 208C 208A Pin Name 95 R13 / PTC3 P13 / PTC4 U14 / PTC5 T14 /PTC6 ...
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Pin No. FP- TBP- 208C 208A Pin Name 121 L14 AUDATA3/PTF3/TO3 122 L15 /PTJ0 123 L16 /PTJ1 124 L17 /PTJ2 125 K14 /PTJ3 ...
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Pin No. FP- TBP- 208C 208A Pin Name 151 D15 Vss-PLL2 152 C17 Vcc-PLL2 153 C16 MD5 154 D14 XTAL 155 B17 EXTAL 156 B16 VssQ 157 A17 STATUS0/PTE4 158 A16 STATUS1/PTE5 ...
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Pin No. FP- TBP- 208C 208A Pin Name 180 A10 VssQ 181 D9 / SCPT5 182 B9 Vss 183 184 C9 Vcc 185 A8 IRQ0/ / PTH0 I R ...
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The input level of the details, refer to section 23.4.2, Reset Configuration. 3. These pins are initialized to the general input port setting in which the pull-up MOS is off at a power-on reset. When these pins are connected ...
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Pin Functions Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classification Symbol Power supply Vcc Vss VccQ VssQ Clock Vcc-PLL1 Vss-PLL1 Vcc-PLL2 Vss-PLL2 EXTAL XTAL CKIO I/O Name Function Power supply Power supply for the internal modules ...
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Classification Symbol Operating mode MD6 to MD0 control System control STATUS1, STATUS0 Interrupts NMI IRQ5 to IRQ0 to I ...
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Classification Symbol Bus control , RD ...
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Classification Symbol Direct memory DREQ0, access controller DREQ1 (DMAC) DACK0, DACK1 TEND0 Timer unit (TMU) TCLK 16-bit timer pulse TO3 to TO0 unit (TPU) Serial TxD0, TxD2 communication RxD0, RxD2 interface with SCK0, SCK2 FIFO (SCIF0, SCIF2 ...
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Classification Symbol USB EXTAL_USB XTAL_USB XVDATA VBUS TXDPLS TXDMNS DPLS DMNS TXENL SUSPND Vcc-USB Vss-USB D D I/O Name Function I USB clock USB clock input pin. (48-MHz input) O USB clock USB clock pin. I Data input Receive data ...
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Classification Symbol I/O port PTA7 to PTA0 PTB7 to PTB0 PTC7 to PTC0 PTD7 to PTD0 PTE7 to PTE0 PTF7 to PTF0 PTG7 to PTG0 PTH6 to PTH0 PTJ7 to PTJ0 PTK7 to PTK0 PTL3 to PTL0 PTM6, PTM4 to ...
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Classification Symbol User debugging TCK interface TMS (UDI) TDI TDO Advanced user AUDATA3 to AUDATA0 debugger (AUD) AUDCK AUDSYNC E10A interface I/O ...
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Rev. 2.00, 09/03, page 24 of 690 ...
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Processing States and Processing Modes 2.1.1 Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the CPU processing states. Reset ...
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Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD bit is cleared to 0, the ...
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Memory Map 2.2.1 Logical Address Space The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of logical address space. User programs and data are accessed from the logical address space. The logical address space is ...
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Table 2.1 Logical Address Space Address Range Name H’00000000 to P0/U0 H’7FFFFFFF P1 H’80000000 to H’9FFFFFFF H’A0000000 to P2 H’BFFFFFFF H’C0000000 to P3 H’DFFFFFFF P4 H’E0000000 to H’FFFFFFFF 2.2.2 External Memory Space The LSI uses 29 bits of the 32-bit ...
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H'0000 0000 P0 area H'8000 0000 P1 area H'A000 0000 P2 area H'C000 0000 P3 area H'E000 0000 P4 area H'FFFF FFFF Privileged mode Figure 2.2 Logical Address to External Memory Space Mapping 2.3 Register Descriptions This LSI provides thirty-three ...
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Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each process mode. Table 2.2 Register Initial Values Register Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 R15 System registers MACH, ...
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R0_BANK0 *2 R1_BANK0 *2 R2_BANK0 *2 R3_BANK0 *2 R4_BANK0 *2 R5_BANK0 *2 R6_BANK0 *2 R7_BANK0 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC (a) User mode register configuration Notes: 1. The ...
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General Registers There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15 are banked. The process mode and the register bank (RB) bit in the status register (SR) define which ...
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R10 R11 R12 R13 R14 R15 2.3.2 System Registers The system registers: multiply and accumulate registers (MACH/MACL) and procedure register ...
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Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. There is no instruction to read the PC directly. Before an exception handling state is entered, the PC is saved in ...
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Control Registers The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC instruction in privileged mode. The GBR register can be accessed in the user mode. The control registers are described below. ...
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Initial Bit Bit Name Value R/W Note: The and T bits can be ...
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Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged mode transition from reset state to exception handling state occurs, this register is referenced as a base address. For details, refer to section ...
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Memory Data Formats Memory data formats are classified into byte, word, and longword. Memory can be accessed in byte, word, and longword. When the memory operand is only a byte (8 bits word (16 bits ...
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The little endian mode can also be specified as data format. Either big-endian or little-endian mode can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor operates in big-endian mode. When MD5 ...
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Features of CPU Core Instructions 2.5.1 Instruction Execution Method Instruction Length: All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one ...
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Literal Constant: Byte literal constant is placed inside the instruction code as immediate data. Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in ...
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CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions Addressing Instruction Mode Format Rn Register direct ...
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Addressing Instruction Mode Format Indexed @(R0, Rn) Effective address is sum of register Rn and R0 register indirect GBR indirect @(disp:8, GBR) with displacement Indexed GBR @(R0, indirect GBR) PC-relative with @(disp:8, displacement PC) Effective Address Calculation Method contents. Rn ...
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Addressing Instruction Mode Format PC-relative disp:8 disp:12 Rn Immediate #imm:8 #imm:8 #imm:8 Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or x4) ...
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CPU Instruction Formats Table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are ...
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Instruction Format nm type 15 0 xxxx nnnn xxxx mmmm md type 15 0 xxxx xxxx dddd mmmm nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn dddd mmmm Rev. 2.00, 09/03, page 46 of ...
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Instruction Format d type 15 0 xxxx xxxx dddd dddd d12 type 15 0 xxxx dddd dddd dddd nd8 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx ...
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Instruction Set 2.6.1 CPU Instruction Set Based on Functions The CPU instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. Tables 2.6 to 2.11 show the instruction notation, machine code, ...
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Kinds of Type Instruction Arithmetic 21 operation instructions Logic 6 operation instructions Shift 12 instructions Op Code Function MULS Signed multiplication (16 MULU Unsigned multiplication (16 NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction ...
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Kinds of Type Instruction Branch 9 instructions System 15 control instructions Total: 68 Rev. 2.00, 09/03, page 50 of 690 Op Code Function BF Conditional branch, delayed conditional branch ( Conditional branch, delayed conditional branch (T = ...
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The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Instruction Code Indicated by mnemonic. Indicated in MSB LSB order. Explanation ...
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Table 2.6 Data Transfer Instructions Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn 0110nnnnmmmm0011 MOV.B Rm,@Rn 0010nnnnmmmm0000 MOV.W Rm,@Rn 0010nnnnmmmm0001 MOV.L Rm,@Rn 0010nnnnmmmm0010 MOV.B @Rm,Rn 0110nnnnmmmm0000 MOV.W @Rm,Rn 0110nnnnmmmm0001 MOV.L @Rm,Rn 0110nnnnmmmm0010 MOV.B ...
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Instruction Instruction Code Operation MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT Rn 0000nnnn00101001 SWAP.B Rm,Rn 0110nnnnmmmm1000 ...
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Table 2.7 Arithmetic Operation Instructions Instruction Instruction Code Operation ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL ...
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Instruction Instruction Code Operation EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+, 0000nnnnmmmm1111 @Rn+ MAC.W @Rm+, 0100nnnnmmmm1111 @Rn+ MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB ...
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Table 2.8 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0, 11001101iiiiiiii GBR) NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0, 11001111iiiiiiii GBR) TAS.B @Rn 0100nnnn00011011 TST Rm,Rn 0010nnnnmmmm1000 TST #imm,R0 11001000iiiiiiii ...
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Table 2.9 Shift Instructions Instruction Instruction Code Operation ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm, Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm, Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 ...
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Table 2.10 Branch Instructions Instruction Instruction Code Operation BF disp 10001011dddddddd BF/S disp 10001111dddddddd BT disp 10001001dddddddd BT/S disp 10001101dddddddd BRA disp 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR disp 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 ...
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Table 2.11 System Control Instructions Instruction Instruction Code Operation CLRM 0000000000101000 AC CLRS 0000000001001000 CLRT 0000000000001000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC Rm,SSR 0100mmmm00111110 LDC Rm,SPC 0100mmmm01001110 LDC Rm,R0_BANK 0100mmmm10001110 LDC Rm,R1_BANK 0100mmmm10011110 LDC Rm,R2_BANK 0100mmmm10101110 ...
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Instruction Instruction Code Operation LDC.L @Rm+, 0100mmmm11100111 R6_BANK LDC.L @Rm+, 0100mmmm11110111 R7_BANK LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 LDS.L @Rm+,MACL 0100mmmm00010110 LDS.L @Rm+,PR 0100mmmm00100110 LDTLB 0000000000111000 NOP 0000000000001001 PREF @Rm 0000mmmm10000011 RTE 0000000000101011 SETS ...
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Instruction Instruction Code STC.L SSR,@–Rn 0100nnnn00110011 STC.L SPC,@–Rn 0100nnnn01000011 STC.L R0_BANK,@–Rn 0100nnnn10000011 STC.L R1_BANK,@–Rn 0100nnnn10010011 STC.L R2_BANK,@–Rn 0100nnnn10100011 STC.L R3_BANK,@–Rn 0100nnnn10110011 STC.L R4_BANK,@–Rn 0100nnnn11000011 STC.L R5_BANK,@–Rn 0100nnnn11010011 STC.L R6_BANK,@–Rn 0100nnnn11100011 STC.L R7_BANK,@–Rn 0100nnnn11110011 STS MACH,Rn 0000nnnn00001010 STS MACL,Rn 0000nnnn00011010 STS ...
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Operation Code Map Table 2.12 shows the operation code map. Table 2.12 Operation Code Map Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC 0000 Rn 01MD ...
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Instruction Code Fx: 0000 MSB LSB MD: 00 0011 Rn Rm 01MD DIV1 0011 Rn Rm 10MD SUB 0011 Rn Rm 11MD ADD 0100 Rn Fx 0000 SHLL 0100 Rn Fx 0001 SHLR 0100 Rn Fx 0010 STS.L 0100 Rn ...
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Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rn Rm 1100 SHAD 0100 Rn Rm 1101 SHLD 0100 Rm 00MD 1110 LDC 0100 Rm 01MD 1110 LDC 0100 Rm 10MD 1110 LDC 0100 Rm 11MD 1110 LDC 0100 Rn ...
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Section 3 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that supports a virtual memory system. The on-chip translation look-aside buffer (TLB) caches information for user-created address translation tables located in external memory. It enables ...
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For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. ...
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MMU of This LSI Virtual Address Space: This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As shown in figures 3.2 and 3.3, the virtual address space is divided into several areas. ...
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H'0000 0000 Area P0 cacheable address translation possible H'8000 0000 Area P1 cacheable address translation not possible H'A000 0000 Area P2 non-cacheable address translation not possible H'C000 0000 Area P3 cacheable address translation possible H'E000 0000 Area P4 non-cacheable ...
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H'0000 0000 Area P0 cacheable H'8000 0000 Area P1 cacheable H'A000 0000 Area P2 non-cacheable H'C000 0000 Area P3 cacheable H'E000 0000 Area P4 non-cacheable H'FFFF FFFF Privileged mode Figure 3.3 Virtual Address Space (MMUCR. H'F000 0000 H'F100 ...
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The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For more information, see section 4.4, Memory-Mapped Cache. The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache ...
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Address Transition: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to ...
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In single virtual memory mode, the ASID is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 3.3.3, TLB Address Comparison). 3.2 Register Descriptions There are four registers for MMU processing. ...
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Page Table Entry Register Low (PTEL) The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB ...
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Bit Initial Bit Name Value Rev. 2.00, 09/03, page 74 of 690 R/W Description R Reserved ...
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TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the logical page number and the corresponding physical number, the address space identifier, and the ...
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VPN (31-17) Legend: VPN: Virtual page number Upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page. Since VPN bits are used as ...
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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits are used as the index number regardless of the page size. The index number can be generated ...
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Virtual address 31 Index 0 VPN(31-17) 31 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory ...
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The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page-size information determines whether VPN (11 to ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., ...
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MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the ...
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MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR ...
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Avoiding Synonym Problems When 4-kbyte page is recorded in a TLB entry, a synonym problem may arise number of virtual addresses are mapped onto a single physical address, the same physical address data will ...
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The above restrictions apply only when performing accesses using the cache. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to ...
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MMU Exceptions When the address translation unit of the MMU is enabled, occurrence of the MMU exception is checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial ...
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If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return ...
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TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid ...
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Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is ...
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CPU address error No VPNs match? Yes TLB miss exception User mode PR? 00/ R/W? R TLB protection violation exception No (Non-cacheable) Initial page write exception Memory access Figure 3.13 MMU Exception Generation Flowchart Start Yes Address error? ...
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Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual ...
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TLB address array access • Read access Address field 31 Data field • Write access Address field 31 Data field VPN: ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 3000 ; MMUCR.IX=0 ; the V ...
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Features Capacity kbytes Structure: Instructions/data mixed, 4-way set associative Locking: Way 2 and way 3 are lockable Line size: 16 bytes Number of entries: 256 entries/way in 16-kbyte mode or 512 entries/way in 32-kbyte mode Write ...
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Address array (ways 0−3) Entry Tag address Entry Entry 511 22) bits Figure 4.1 Cache Structure (32-kbyte Mode) Address Array: The V bit indicates whether ...
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Table 4.2 LRU and Way Replacement (when Cache Locking Mechanism Is Disabled) LRU (Bits 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, ...
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Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which invalidates all cache entries), and WT and CB bits (which select either write-through mode or ...
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Cache Control Register 2 (CCR2) The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU enters the cache lock mode when the lock enable bit (bit 16) in the cache control register 2 (CCR2) ...
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Bit Initial Bit Name Value — — W3LOAD 0 8 W3LOCK — W2LOAD 0 0 W2LOCK 0 Note: W2LOAD and W3LOAD should ...
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Table 4.3 Way Replacement when a PREF Instruction Misses the Cache DSP Bit W3LOAD W3LOCK Notes: * Don’t care ...
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Table 4.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1) LRU (Bits 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, ...
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Operation 4.3.1 Searching the Cache If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1, P3, and U0 are accessed the cache will be searched to see if the ...
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Read Access Read Hit read access, instructions and data are transferred from the cache to the CPU. The s LRU i updated to indicate that the hit way is the most recently hit way. Read Miss: An ...
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Write-Back Buffer When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to ...
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Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array ...
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LRU bits remain unchanged. When there is no way that receives a hit, nothing is written and there is no operation. This operation is used to invalidate the address specification for a cache. When the U bit of ...
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Address array access (a) Address specification Read access 31 24 1111 0000 Write access 31 24 1111 0000 (b) Data specification (both read and write accesses) 31 Tag address (31 to 10) (2) Data array access (both read and ...
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Usage Examples Invalidating a Specific Entry: A specific cache entry can be invalidated by accessing the allocated memory cache and writing the entry’s U and V bits. The A bit is cleared to 0, and an ...
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Invalidating an Address Specification: An address specification can be invalidated by accessing the memory allocation cache and writing the entry’s V bit. When the A bit is 1, the tag address specified by the write data is ...
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Section 5 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example attempt is made to execute an undefined instruction code or an instruction protected ...
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Figure 5.1 shows the bit configuration of each register Figure 5.1 Register Bit Configuration 5.1.1 TRAPA Exception Register (TRA) TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the ...
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Exception Event Register (EXPEVT) EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified the hardware ...
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Interrupt Event Register 2 (INTEVT2) INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware ...
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Exception Handling Function 5.2.1 Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the ...
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The above operations from are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction, a status different from that in effect before the ...
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To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before ...
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An exception caused by an instruction decode (General illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type exception related to data access (CPU address error and MMU related exceptions: re- execution type) ...
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Exception Current Type Instruction Exception Event TLB invalid * General Re-executed exception events TLB protection violation * (data access) Initial page write * (data access) Completed Unconditional trap (TRAPA instruction) User breakpoint (After instruction execution, address) General Completed User breakpoint ...
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Individual Exception Operations This section describes the conditions for specific exception handling and the processor operations for resets and general exceptions. For interrupts, refer to section 6, Interrupt Controller (INTC). 5.3.1 Resets Power-On Reset: Conditions Power-on reset is request ...
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Exception code An exception occurred during read: H'0E0 An exception occurred during write: H'1E0 Remarks The logical address (32 bits) that caused the exception is set in TEA. Illegal General Instruction Exception: Conditions When undefined code not in a delay ...
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Save address A delayed branch instruction address Exception code H'1A0 Remarks None Unconditional Trap: Conditions TRAPA instruction executed Types Instruction synchronous, processing-completion type Save address An address of an instruction following TRAPA Exception code H'160 Remarks The exception is a ...
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Remarks For details on user break controller, refer to section 22, User Break Controller (UBC). DMA Address Error: Conditions Word data accessed from addresses other than word boundaries ( Longword accessed from addresses other than ...
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Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) Exception code An ...
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Exception code An exception occurred during read: H'0A0 An exception occurred during write: H'0C0 Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. Initial Page Write Exception: Conditions A ...
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Usage Notes 1. An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests ...
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Figure 6.1 shows a block diagram of the INTC. NMI IRQ5−IRQ0 6 PINT15−PINT0 16 (Interrupt request) DMAC SCIF ADC USB TMU TPU WDT UDI REF RTC Legend: DMAC : Direct memory access controller SCIF : Serial communication interface (with FIFO) ...
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Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Nonmaskable interrupt input pin Interrupt input pins Port interrupt input pins Note: to are multiplexed with IRQ3 to IRQ0; they cannot be used together with ...
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Interrupt Priority Level Setting Registers (IPRA to IPRH) IPRA to IPRH are 16-bit readable/writable registers in which priority levels from are set for on-chip peripheral module, and IRQ and PINT interrupts. Bit Bit ...
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Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. Bit Bit Name Initial Value 0/1 * ...
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Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, high level, or low level. Bit Bit Name Initial Value 15 ...
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Bit Bit Name Initial Value IRQ51S to 0 IRQ00S R/W Description R/W IRQn Sense Select Select whether the interrupt signals to the IRQ5 to IRQ0 pins are detected at the falling edge, at the rising edge, at ...
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Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT15 to PINT0. Bit Bit Name Initial Value PINT15S to 0 PINT0S 6.3.5 PINT Interrupt Enable ...
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Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. Bit Bit Name Initial Value 7 PINT0R 0 6 PINT1R ...
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Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit register that indicates whether DMAC or SCIF0 interrupt requests are generated. Bit Initial Bit Name Value R/W 7 TXI0R RXI0R ERI0R ...
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Bit Initial Bit Name Value R/W 0 DEI0R 0 R 6.3.8 Interrupt Request Register 2 (IRR2) IRR2 is an 8-bit register that indicates whether SCIF2 or ADC interrupt requests are generated. Bit Initial Bit Name Value R ...
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Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an ...
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IRL Interrupts IRL interrupts are input by level at pins indicated by pins interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority ...
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Table 6.3 to Pins and Interrupt Levels ...
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USB interface (USB) Timer unit (TMU) 16-bit timer pulse unit (TPU) Watchdog timer (WDT) Bus state controller (BSC) User-debugging interface (UDI) Realtime clock (RTC) Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt ...
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Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Code * Interrupt Source H'1C0 * NMI H'5E0 * UDI H'600 * IRQ IRQ0 H'620 * IRQ1 H'640 * IRQ2 H'660 * IRQ3 H'680 * IRQ4 H'6A0 * IRQ5 ...
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Interrupt Code * Interrupt Source H'400 * TMU0 TUNI0 H'420 * TMU1 TUNI1 H'440 * TMU2 TUNI2 H'460 * TICPI2 H'480 * RTC ATI H'4A0 * PRI H'4C0 * CUI H'560 * WDT ITI H'580 * REF RCMI Notes: 1. ...
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Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Code * Interrupt Source H'1C0 * NMI H'5E0 * UDI ( 3:0) = 0000 H'200 * IRL 3:0) = 0001 H'220 * ...
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Interrupt Code * Interrupt Source H'900 * SCIF2 ERI2 H'920 * RXI2 H'960 * TXI2 H'980 * ADC ADI H'A20 * USB USI0 H'A40 * USI1 H'C00 * TPU0 TPI0 H'C20 * TPU1 TPI1 H'C80 * TPU2 TPI2 H'CA0 * ...
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Table 6.6 Interrupt Level and INTEVT Code Interrupt level 6.5 Operation 6.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 6.3 is ...
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The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and ...
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No ICR1.BLMSK = 1? No Yes NMI? No Yes NMI? Yes Set interrupt source in INTEVT and INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bits Branch to exception handler I3-I0: Interrupt mask ...
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Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT or INTEVT2. The code in INTEVT or INTEVT2 can be used ...
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Rev. 2.00, 09/03, page 148 of 690 ...
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Section 7 Bus State Controller (BSC) 7.1 Overview The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly ...
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Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 7.1.2 Block Diagram BSC functional block diagram is shown in figure 7.1. CS0, CS2, CS3, CS4, CS5A, ...
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Pin Configuration Table 7.1 Pin Configuration Name I/O A25 D31 ...
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Name I/O CKE MD3, MD4 I MD5 I 7.3 Area Overview In the architecture of this LSI, both logical spaces and ...