HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet
HD6417032F20V
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HD6417032F20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7032, SH7034 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH7030 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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The SH7032 and SH7034 are microprocessors that integrate peripheral functions necessary for system configuration with a 32-bit internal architecture SH1-DSP CPU as its core. The SH7032 and SH7034's on-chip peripheral functions include an interrupt controller, timers, serial communication interfaces, a ...
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User's Manuals on the SH7032 and SH7034: Manual Title SH7032 and SH7034 Hardware Manual SH-1, SH-2, SH-DSP Software Manual Users manuals for development tools: Manual Title C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual High-performance Embedded ...
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Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the sections within this manual. Table 1 Manual Organization Category Section Title Overview 1. Overview CPU 2. CPU Operating 3. Operating Modes ...
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Category Section Title Data 13. Serial Processing Communication Interface 14. A/D Converter Pins 15. Pin Function Controller 16. Parallel I/O Ports Memory 17. ROM 18. RAM Power-Down 19. Power-Down State State Electrical 20. Electrical Characteristics Characteristics Rev. 7.00 Jan 31, ...
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CPU 7. Clock pulse generator (CPG) Buses 8. Bus state controller (BSC) 9. Direct memory access controller (DMAC) Memory 17. ROM 18. RAM Pins 15. Pin function controller (PFC) 16. Parallel I/O ports Figure 1 Manual Organization 1. Overview ...
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Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas ...
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List of Items Revised or Added for This Version Item Page All 1.1 SuperH 6 Microcomputer Features Table 1.2 Product Lineup 2.3.2 Addressing 27 Modes Table 2.8 Addressing Modes and Effective Addresses 2.3.3 Instruction 28 Formats Table 2.9 Instruction Formats ...
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Item Page 2.4.1 Instruction 37 Set by Classification Table 2.13 Arithmetic Instructions 2.4.2 Operation 42, 43 Code Map Table 2.18 Operation Code Map 8.5.3 Wait State 151 Control 10.4.5 Reset- 273 Synchronized PWM Mode Figure 10.31 Procedure for Selecting Reset- ...
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Item Page 20.1.3 AC 486 Characteristics (3) Bus Timing Figure 20.9 Basic Bus Cycle: Two- State Access Figure 20.12 (b) 490 DRAM Bus Cycle (Short-Pitch, High- Speed Page Mode: Write) 20.1.3 AC 502 Characteristics (3) Bus Timing Figure 20.22 Basic ...
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Item Page 20.2.3 AC 538 Characteristics (3) Bus Timing Figure 20.53 Basic Bus Cycle: Two- State Access Figure 20.56 (b) 542 DRAM Bus Cycle (Short-Pitch, High- Speed Page Mode: Write) Rev Jan 31, 2006 page xii of xxvi ...
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Section 1 Overview ............................................................................................................. 1.1 SuperH Microcomputer Features ...................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Descriptions ................................................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 11 1.3.3 Pin Layout by Mode............................................................................................. 15 Section 2 CPU ...................................................................................................................... 17 2.1 Register Configuration ...
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Section 4 Exception Handling 4.1 Overview........................................................................................................................... 51 4.1.1 Exception Handling Types and Priorities ............................................................ 51 4.1.2 Exception Handling Operation............................................................................. 53 4.1.3 Exception Vector Table ....................................................................................... 54 4.2 Resets ................................................................................................................................ 56 4.2.1 Reset Types.......................................................................................................... 56 4.2.2 Power-On Reset ................................................................................................... 57 4.2.3 ...
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On-Chip Interrupts ............................................................................................... 71 5.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 71 5.3 Register Descriptions ........................................................................................................ 74 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) ................................................... 74 5.3.2 Interrupt Control Register (ICR) .......................................................................... 75 5.4 Interrupt Operation............................................................................................................ 76 5.4.1 Interrupt ...
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Features................................................................................................................ 103 8.1.2 Block Diagram..................................................................................................... 104 8.1.3 Pin Configuration................................................................................................. 105 8.1.4 Register Configuration......................................................................................... 106 8.1.5 Overview of Areas ............................................................................................... 107 8.2 Register Descriptions ........................................................................................................ 109 8.2.1 Bus Control Register (BCR) ................................................................................ 109 8.2.2 Wait State Control Register 1 (WCR1)................................................................ ...
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Wait State Control............................................................................................................. 166 8.10 Bus Arbitration.................................................................................................................. 169 8.10.1 Operation of Bus Arbitration ............................................................................... 170 8.10.2 BACK Operation ................................................................................................. 171 8.11 Usage Notes ...................................................................................................................... 172 8.11.1 Usage Notes on Manual Reset ............................................................................. 172 8.11.2 Usage Notes on Parity Data ...
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Input/Output Pins ................................................................................................. 231 10.1.4 Register Configuration......................................................................................... 232 10.2 ITU Register Descriptions ................................................................................................ 234 10.2.1 Timer Start Register (TSTR) ............................................................................... 234 10.2.2 Timer Synchro Register (TSNC) ......................................................................... 235 10.2.3 Timer Mode Register (TMDR) ............................................................................ 237 10.2.4 Timer Function Control ...
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Contention Between Counter Clearing by Input Capture and Counter Increment................................................................................................ 300 10.6.8 Contention between General Register Write and Input Capture .......................... 301 10.6.9 Note on Waveform Cycle Setting ........................................................................ 301 10.6.10 Contention between BR Write and Input Capture................................................ 302 ...
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Pin Configuration................................................................................................. 340 12.1.4 Register Configuration......................................................................................... 341 12.2 Register Descriptions ........................................................................................................ 341 12.2.1 Timer Counter (TCNT)........................................................................................ 341 12.2.2 Timer Control/Status Register (TCSR)................................................................ 342 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 343 12.2.4 Notes on Register Access..................................................................................... 344 12.3 Operation .......................................................................................................................... ...
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SCI Interrupt Sources and the DMAC .............................................................................. 407 13.5 Usage Notes ...................................................................................................................... 407 Section 14 A/D Converter 14.1 Overview........................................................................................................................... 411 14.1.1 Features ................................................................................................................ 411 14.1.2 Block Diagram ..................................................................................................... 412 14.1.3 Configuration of Input Pins.................................................................................. 413 14.1.4 Configuration of A/D ...
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Port A Data Register (PADR).............................................................................. 448 16.3 Port B ................................................................................................................................ 449 16.3.1 Register Configuration......................................................................................... 449 16.3.2 Port B Data Register (PBDR) .............................................................................. 450 16.4 Port C ................................................................................................................................ 451 16.4.1 Register Configuration......................................................................................... 451 16.4.2 Port C Data Register (PCDR) .............................................................................. ...
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AC Characteristics ............................................................................................... 477 (1) Clock Timing................................................................................................. 477 (2) Control Signal Timing................................................................................... 479 (3) Bus Timing.................................................................................................... 482 (4) DMAC Timing .............................................................................................. 512 (5) 16-bit Integrated Timer Pulse Unit Timing ................................................... 514 (6) Programmable Timing Pattern Controller and I/O Port ...
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A.2.10 Timer Start Register (TSTR) ITU........................................................................ 577 A.2.11 Timer Synchronization Register (TSNC) ITU..................................................... 578 A.2.12 Timer Mode Register (TMDR) ITU .................................................................... 580 A.2.13 Timer Function Control Register (TFCR) ITU.................................................... 581 A.2.14 Timer Control Registers 0–4 (TCR0–TCR4) ITU ............................................... 582 A.2.15 ...
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A.2.50 Timer Control/Status Register (TCSR) WDT...................................................... 621 A.2.51 Timer Counter (TCNT) WDT.............................................................................. 623 A.2.52 Reset Control/Status Register (RSTCSR) WDT .................................................. 623 A.2.53 Standby Control Register (SBYCR) Power-Down State ..................................... 624 A.2.54 Port A Data Register (PADR) Port A .................................................................. 625 ...
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Rev. 7.00 Jan 31, 2006 page xxvi of xxvi ...
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SuperH Microcomputer Features SuperH microcomputers (SH7000 series) comprise a new generation of reduced instruction set computers (RISC) in which a Renesas-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has ...
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Section 1 Overview Table 1.1 Features of the SH7032 and SH7034 Microcomputers Feature Description CPU Original Renesas architecture 32-bit internal data paths General-register machine: Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction set: Instruction ...
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Feature Description Nine external interrupt pins (NMI, IRQ0–IRQ7) Interrupt controller (INTC) Thirty-one internal interrupt sources Sixteen programmable priority levels User break controller Generates an interrupt when the CPU or DMAC generates a bus cycle (UBC) with specified conditions Simplifies configuration ...
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Section 1 Overview Feature Description Direct memory Permits DMA transfer between the following modules: access External memory controller (DMAC) External I/O (4 channels) On-chip memory Peripheral on-chip modules (except DMAC) DMA transfer can be requested from external pins, on-chip SCI, ...
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Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): Port A: 16 input/output lines (input or output can be selected for each bit) Port B: 16 input/output lines (input or output can be selected ...
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Section 1 Overview Table 1.2 Product Lineup Product On-Chip Operating Operating Number ROM Voltage Frequency SH7032 ROMless 5 MHz 3 12.5 MHz -20 to +75 C SH7034 PROM 5 ...
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Product On-Chip Operating Operating Number ROM Voltage Frequency 1 SH7034B * Mask 3 12.5 MHz -20 to +75 C ROM ROMless 3 MHz Notes: 1. The electrical characteristics of the SH7034B mask ROM ...
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Section 1 Overview 1.2 Block Diagram RES WDTOVF MD2 MD1 MD0 NMI CK EXTAL XTAL * ...
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Pin Descriptions 1.3.1 Pin Arrangement ref PC0/AN0 87 PC1/AN1 88 PC2/AN2 89 PC3/AN3 PC4/AN4 92 PC5/AN5 93 PC6/AN6 94 PC7/AN7 PB0/TP0/TIOCA2 97 PB1/TP1/TIOCB2 ...
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Section 1 Overview ref PC0/AN0 93 PC1/AN1 94 PC2/AN2 95 PC3/AN3 PC4/AN4 99 PC5/AN5 100 PC6/AN6 101 PC7/AN7 V 102 SS PB0/TP0/TIOCA2 103 *3 NC 104 PB1/TP1/TIOCB2 105 106 V ...
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Pin Functions Table 1.3 describes the pin functions. Table 1.3 Pin Functions Pin No. (PRQP0112 Type Symbol JA-A) Power V 15, 43, 70 83, 84 12, 22, SS 31, 40, 52, ...
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Section 1 Overview Pin No. (PRQP0112 Type Symbol JA-A) Operating MD2, 82, 81, 80 mode MD1, control MD0 Interrupts NMI 76 IRQ0– 66–69, 111, 112 IRQ7 IRQOUT 63 Address A21–A0 47–44, 42, bus 41, 39–32, 30–23 Data bus ...
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Pin No. (PRQP0112 Type Symbol JA-A) WAIT Bus control 56 (cont) RAS 54 CASH 49 CASL WRH 58 WRL 57 CS0– 48–51, CS7 53– HBS, 23, 58 LBS WR 57 DREQ0, DMAC 67, 69 DREQ1 ...
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Section 1 Overview Pin No. (PRQP0112 Type Symbol JA-A) TIOCA4, 102, 103 16-bit TIOCB4 integrated timer pulse TOCXA4, 104, 105 unit (ITU) TOCXB4 TCLKA– 66, 67, 104, TCLKD 105 TP15– Timing TP0 112–107, pattern 105–100, controller 98, 97 ...
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Pin Layout by Mode Table 1.4 Pin Layout by Mode Pin No. Pin No. (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode — PB14/TP14/IRQ6 PB15/TP15/IRQ7 AD0 5 ...
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Section 1 Overview Pin No. Pin No. (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode 60 65 PA7/BACK PA8/BREQ 63 68 PA9/AH/IRQOUT/ ADTRG 64 69 PA10/DPL/ TIOCA1 65 70 PA11/DPH/ TIOCB1 66 71 PA12/IRQ0/ DACK0/TCLKA 67 ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data ...
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Section 2 CPU 2.1.2 Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for ...
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System Registers System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. ...
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Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when ...
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Immediate Data Format Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data. Immediate data accessed by the TST, ...
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Section 2 CPU Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded into to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. ...
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Table 2.5 Immediate Data Accessing Classification SH7000 Series CPU 8-bit immediate MOV 16-bit immediate MOV.W ......... .DATA.W H'1234 32-bit immediate MOV.L ......... .DATA.L H'12345678 Note: The address of the immediate data is accessed by @(disp, PC). Absolute Address: When data ...
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Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses Addressing Mnemonic Mode Expression Direct Rn register addressing Indirect @Rn register addressing Post-incre- @Rn + ment ...
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Addressing Mnemonic Mode Expression Indirect @(disp:4, Rn) register addressing with displace- ment Indirect @(R0, Rn) indexed register addressing Indirect @(disp:8, GBR GBR) addressing with displace- ment Indirect @(R0, GBR) indexed GBR addressing Effective Addresses Calculation The effective address is Rn ...
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Section 2 CPU Addressing Mnemonic Mode Expression PC relative @(disp:8, PC) addressing with dis- placement PC relative disp:8 addressing disp:12 Rev. 7.00 Jan 31, 2006 page 26 of 658 REJ09B0272-0700 Effective Addresses Calculation The effective address is the PC value ...
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Addressing Mnemonic Mode Expression PC relative Rn addressing Immediate #imm:8 addressing #imm:8 #imm:8 2.3.3 Instruction Formats The instruction format refers to the source operand and the destination operand. The meaning of the operand depends on the instruction code. Symbols are ...
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Section 2 CPU Table 2.9 Instruction Formats Instruction Format 0 format 15 xxxx xxxx xxxx xxxx n format 15 xxxx nnnn xxxx xxxx m format 15 xxxx mmmm xxxx xxxx Rev. 7.00 Jan 31, 2006 page 28 of 658 REJ09B0272-0700 ...
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Instruction Format nm format 15 xxxx nnnn xxxx mmmm md format 15 xxxx xxxx dddd mmmm nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn mmmm dddd Destination Source Operand Operand mmmm: Register nnnn: Register direct direct ...
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Section 2 CPU Instruction Format d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx ...
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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions Classifi- Operation cation Types Code Data 5 MOV transfer MOVA MOVT SWAP XTRCT Arithmetic 17 ADD operations ADDC ADDV CMP/cond DIV1 ...
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Section 2 CPU Classifi- Operation cation Types Code Logic oper- 6 TST ations XOR (cont) Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BSR JMP JSR RTS System 11 CLRT control ...
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The following tables (arranged by instruction classification) show instruction codes, operations, and execution states, using the format shown below. Table 2.11 Instruction Code Format Item Format Instruction SRC,DEST OP: Operation code OP.Sz mnemonic Instruction MSB LSB code Operation , summary ...
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Section 2 CPU Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L ...
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Instruction MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd R0 MOV.W R0,@(disp,GBR) 11000001dddddddd R0 MOV.L R0,@(disp,GBR) 11000010dddddddd R0 MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) MOV.W @(disp,GBR),R0 11000101dddddddd (disp MOV.L ...
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Section 2 CPU Table 2.13 Arithmetic Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 ...
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Instruction Instruction Code EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MULS Rm,Rn 0010nnnnmmmm1111 MULU Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: * The normal ...
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Section 2 CPU Table 2.14 Logic Operation Instructions Instruction Instruction Code 0010nnnnmmmm1001 Rn & Rm AND Rm,Rn 11001001iiiiiiii R0 & imm AND #imm,R0 AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm 0110nnnnmmmm0111 ~Rm NOT Rm,Rn 0010nnnnmmmm1011 ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Section 2 CPU Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS ...
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Instruction Instruction Code STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Notes: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. ...
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Section 2 CPU 2.4.2 Operation Code Map Table 2.18 shows an operation code map. Table 2.18 Operation Code Map Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn Fx 0010 STC ...
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Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rn Fx 0011 STC.L SR,@–Rn 0100 Rn Fx 0100 ROTL 0100 Rn Fx 0101 ROTR 0100 Rm Fx 0110 LDS.L @Rm+,MACH 0100 Rm Fx 0111 LDC.L @Rm+,SR 0100 Rn Fx 1000 ...
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Section 2 CPU Instruction Code Fx: 0000 MSB MD: 00 LSB 1100 00M imm/disp MOV.B R0,@ D (disp:8,GBR) 1100 01M disp MOV.B D @(disp:8, GBR),R0 1100 10M imm TST D #imm:8,R0 1100 11M imm TST.B D #imm:8, @(R0,GBR) 1101 Rn ...
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CPU State 2.5.1 State Transitions The CPU has five processing states: reset, exception handling, bus-released, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception handling states, ...
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Section 2 CPU From any state when RES = 0 and NMI = 1 Power-on reset state When an interrupt source or DMA address error occurs Bus request Bus-release-state Bus request generated Bus request generated Bus request cleared Sleep mode ...
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Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. ...
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Section 2 CPU 2.5.2 Power-Down State In addition to the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts and power consumption is reduced There are two power-down state modes: sleep mode and ...
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Section 3 Operating Modes 3.1 Types of Operating Modes and Their Selection The SH7032 microcomputer operates in one of two operating modes (modes 0 and 1) and the SH7034 operates in one of four operating modes (modes ...
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Section 3 Operating Modes 3.2.4 Mode 7 (PROM Mode) Mode PROM mode. In this mode, the PROM can be programmed. For details, see section 17, ROM. Mode 7 should only be set for the SH7034 (PROM version). ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priorities As figure 4.1 indicates, exception handling may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two ...
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Section 4 Exception Handling Reset Address error Interrupt Exception source Instruction Notes: 1. The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. 2. The delayed branch instructions are JMP, JSR. BRA. BSR, ...
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Exception Handling Operation Exception sources are detected at the times indicated in table 4.1, whereupon handling starts. Table 4.1 Exception Source Detection and Start of Handling Exception Type Reset Power-on Manual Address error Interrupt Instruction Trap instruction Starts when ...
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Section 4 Exception Handling 4.1.3 Exception Vector Table Before exception handling can execute, the exception vector table must be set in memory. The exception vector table holds the start addresses of exception handling routines (the table for reset exception handling ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset General illegal instruction (Reserved for system use) Illegal slot instruction (Reserved for system use) CPU address error DMA address error Interrupts (Reserved for system use) Trap instruction (user vectors) ...
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Section 4 Exception Handling Table 4.3 Calculation of Exception Vector Table Addresses Exception Source Reset Address error, interrupt, instructions Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table 4.2. 4.2 Resets 4.2.1 Reset Types ...
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Power-On Reset When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state. The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or ...
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Section 4 Exception Handling 4.3 Address Errors 4.3.1 Address Error Sources Address errors occur during instruction fetches and data reading/writing as shown in table 4.5. Table 4.5 Address Error Sources Bus Cycle Type Bus Master Instruction fetch CPU Data read/write ...
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Interrupts 4.4.1 Interrupt Sources Table 4.6 lists the types of interrupt exception handling sources (NMI, user break, IRQ, on-chip supporting module). Table 4.6 Interrupt Sources Interrupt Requesting Pin or Module NMI NMI pin (external input) User break User break ...
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Section 4 Exception Handling Table 4.7 Interrupt Priority Rankings Type NMI User break IRQ and on-chip supporting modules 4.4.3 Interrupt Exception Handling When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always accepted, but other interrupts ...
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Instruction Exceptions 4.5.1 Types of Instruction Exceptions Table 4.8 shows the three types of instruction that start exception handling (trap instructions, illegal slot instructions, and general illegal instructions). Table 4.8 Types of Instruction Exceptions Type Source Instruction Trap instruction ...
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Section 4 Exception Handling 4.5.3 Illegal Slot Instruction An instruction located immediately after a delayed branch instruction is called an “instruction placed in a delay slot.” undefined instruction is located in a delay slot, illegal slot instruction exception ...
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Cases in which Exceptions are Not Accepted In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is ...
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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Table 4.10 shows the stack after exception handling. Table 4.10 Stack after Exception Handling Type Stack Status Address Address of error SP instruction after instruc- tion that has finished executing ...
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Notes 4.8.1 Value of the Stack Pointer (SP) An address error occurs if the stack is accessed for exception handling when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four ...
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Section 4 Exception Handling Rev. 7.00 Jan 31, 2006 page 66 of 658 REJ09BX0272-0700 ...
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Section 5 Interrupt Controller (INTC) 5.1 Overview The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according ...
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Section 5 Interrupt Controller (INTC) IRQOUT NMI IRQ0 IRQ1 Input IRQ2 control IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) ITU (Interrupt request) SCI (Interrupt request) PRT (Interrupt request) A/D (Interrupt request) WDT (Interrupt request) ...
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Pin Configuration INTC pins are summarized in table 5.1. Table 5.1 INTC Pin Configuration Name Nonmaskable interrupt input pin NMI Interrupt request input pins Interrupt request output pin 5.1.4 Registers The interrupt controller has six registers as listed in ...
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Section 5 Interrupt Controller (INTC) 5.2 Interrupt Sources There are four types of interrupt sources: NMI, user break, IRQ, and on-chip supporting module interrupts. Interrupt rankings are expressed as priority levels (0–16), with 0 the lowest and 16 the highest. ...
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On-Chip Interrupts On-chip interrupts are interrupts generated by the following 6 on-chip supporting modules: Direct memory access controller (DMAC) 16-bit integrated timer pulse unit (ITU) Serial communication interface (SCI) Bus state controller (BSC) A/D converter (A/D) Watchdog timer (WDT) ...
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Section 5 Interrupt Controller (INTC) Table 5.3 Interrupt Exception Vectors and Rankings Interrupt Pri- ority Order Interrupt Source (Initial Value) NMI 16 User break 15 IRQ0 0–15 (0) IRQ1 0–15 (0) IRQ2 0–15 (0) IRQ3 0–15 (0) IRQ4 0–15 (0) ...
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Interrupt Pri- ority Order Interrupt Source (Initial Value) ITU3 IMIA3 0–15 (0) IMIB3 OVI3 Reserved ITU4 IMIA4 0–15 (0) IMIB4 OVI4 Reserved SCI0 ERI0 0–15 (0) RxI0 TxI0 TEI0 SCI1 ERI1 0–15 (0) RxI1 TxI1 TEI1 1 PRT * PEI ...
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Section 5 Interrupt Controller (INTC) 5.3 Register Descriptions 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) The five registers IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15 to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources ...
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A reset initializes IPRA–IPRE to H'0000. These registers are not initialized in standby mode. 5.3.2 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input detection mode of external interrupt ...
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Section 5 Interrupt Controller (INTC) Bits 7–0 IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): IRQ0–IRQ7 select whether the falling edge or low level of the IRQ inputs is sensed at pins IRQ0–IRQ7. Bits 7–0: IRQ0S–IRQ7S Description Interrupt is requested when IRQ input is ...
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The CPU accesses the exception vector table at the entry for the vector number of the accepted interrupt, reads the start address of the exception handling routine, branches to that address, and starts executing the program there. This branch ...
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Section 5 Interrupt Controller (INTC) Program execution state No Interrupt? Yes No NMI? Yes User break? Yes IRQOUT low *1 Push SR onto stack Push PC onto stack Copy level of accep- tance from IRQOUT high *2 ...
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Stack after Interrupt Exception Handling Figure 5.3 shows the stack after interrupt exception handling. Address 4n–8 4n–6 4n–4 4n–2 4n Notes: Bus width is 16 bits stores the start address of the next instruction (return instruction) after ...
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Section 5 Interrupt Controller (INTC) 5.5 Interrupt Response Time Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruction of the ...
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Instruction (instruction replaced by interrupt exception handling) Overrun fetch Interrupt service routine— first instruction When m3, the interrupt response time is 11 cycles. F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory access) Note: ...
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Section 5 Interrupt Controller (INTC) Rev. 7.00 Jan 31, 2006 page 82 of 658 REJ09B0272-0700 ...
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Section 6 User Break Controller (UBC) 6.1 Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to ...
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Section 6 User Break Controller (UBC) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the user break controller. Module bus BBR BAMRH BAMRL Break condition comparator User break interrupt generating circuit UBC BARH, BARL: Break address registers H ...
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Register Configuration The user break controller has five registers as listed in table 6.1. These registers are used for setting break conditions. Table 6.1 User Break Controller Registers Name Break address register high Break address register low Break address ...
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Section 6 User Break Controller (UBC) 6.2 Register Descriptions 6.2.1 Break Address Registers (BAR) There are two break address registers—break address register H (BARH) and break address register L (BARL)—that together form a single group. Both are 16-bit read/write registers. ...
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Break Address Mask Register (BAMR) The two break address mask registers—break address mask register H (BAMRH) and break address mask register L (BARML)—together form a single group. Both are 16-bit read/write registers. BAMRH determines which of the bits in ...
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Section 6 User Break Controller (UBC) 6.2.3 Break Bus Cycle Register (BBR) The break bus cycle register (BBR 16-bit read/write register that selects the following four break conditions: CPU cycle or DMA cycle Instruction fetch or data access ...
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Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): ID1 and ID0 select whether to break on instruction fetch and/or data access bus cycles. Bit 5: ID1 Bit 4: ID0 Description break interrupt occurs 1 Break only ...
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Section 6 User Break Controller (UBC) 6.3 Operation 6.3.1 Flow of User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below. 1. Break conditions are set in the break address register ...
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BARH/BARL Internal address bits 31–0 CD1 CD0 CPU cycle DMA cycle ID1 ID0 Instruction fetch Data access RW1 RW0 Read cycle Write cycle SZ1 SZ0 Byte size Word size Longword size Figure 6.2 Break Condition Logic Section 6 User Break ...
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Section 6 User Break Controller (UBC) 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory On-chip memory (on-chip ROM (SH7034 only) and RAM) is always accessed 32 bits each bus cycle. Two instructions are therefore fetched in a bus cycle ...
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Setting User Break Conditions CPU Instruction Fetch Bus Cycle: Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054 Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size not included in conditions) A ...
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Section 6 User Break Controller (UBC) 6.5 Notes 6.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory break condition is set on the second of these two instructions but the contents of the UBC ...
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Instruction Fetch Break If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after ...
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Section 6 User Break Controller (UBC) Rev. 7.00 Jan 31, 2006 page 96 of 658 REJ09B0272-0700 ...
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Section 7 Clock Pulse Generator (CPG) 7.1 Overview The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the chip and external devices with a clock pulse. The CPG makes the chip run at the oscillation frequency of ...
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Section 7 Clock Pulse Generator (CPG =10– Figure 7.2 Connection of Crystal Resonator (Example) Table 7.1 Damping Resistance Frequency [MHz [Ω] 1k Crystal Resonator: Figure 7.3 shows an equivalent circuit of the ...
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External Clock Input An external clock signal can be input at the EXTAL pin as shown in figure 7.4. The XTAL pin should be left open. The frequency must be equal to the system clock (CK) frequency. The specifications ...
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Section 7 Clock Pulse Generator (CPG) 7.3 Usage Notes Board Design: When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Route no other signal lines near the ...
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Input duty * Note: * With the SH7034B, compensation is performed in the input duty range of 60% to 40%. Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics Section ...
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Section 7 Clock Pulse Generator (CPG) Rev. 7.00 Jan 31, 2006 page 102 of 658 REJ09B0272-0700 ...
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Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM, SRAM, ...
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Section 8 Bus State Controller (BSC) Refresh counter can be used as an interval timer Interrupt request generated at compare match (CMI interrupt request signal) 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the bus state controller. WAIT ...
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Pin Configuration Table 8.1 shows the BSC pin configuration. Table 8.1 Pin Configuration Name Abbreviation CS7–CS0 Chip select 7–0 RD Read WRH High write WRL Low write Write HBS * 2 High byte strobe LBS * ...
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Section 8 Bus State Controller (BSC) 8.1.4 Register Configuration The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM interface, and parity check. Table 8.2 Register Configuration Name Bus control register Wait state control ...
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Overview of Areas The SH microprocessors have a 32-bit address space in the architecture, but the upper 4 bits are ignored. Table 8.3 outlines the space divisions. As shown, the space is divided into areas 0–7 according to the ...
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Section 8 Bus State Controller (BSC) Table 8.3 Overview of Space Divisions Area Address 0 H'0000000–H'0FFFFFF 1 H'1000000–H'1FFFFFF 2 H'2000000–H'2FFFFFF 3 H'3000000–H'3FFFFFF 4 H'4000000–H'4FFFFFF 5 H'5000000–H'5FFFFFF 6 H'6000000–H'6FFFFFF 7 H'7000000–H'7FFFFFF 0 H'8000000–H'8FFFFFF 1 H'9000000–H'9FFFFFF 2 H'A000000–H'AFFFFFF 3 H'B000000–H'BFFFFFF 4 H'C000000–H'CFFFFFF ...
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Register Descriptions 8.2.1 Bus Control Register (BCR) The bus control register (BCR 16-bit read/write register that selects the functions of areas and status of bus cycles initialized to H'0000 by a power-on reset, but is ...
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Section 8 Bus State Controller (BSC) Bit 13—Warp Mode Bit (WARP): WARP selects warp or normal mode. 0 sets normal mode and 1 sets warp mode. In warp mode, some external accesses are carried out in parallel with internal access. ...
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Wait State Control Register 1 (WCR1) Wait state control register 16-bit read/write register that controls the number of states for accessing each area and whether wait states are used. WCR1 is initialized to H'FFFF by a ...
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Section 8 Bus State Controller (BSC) 7) finish in 1 state, regardless of the settings of bits RW0 and RW7. The WAIT signal is not sampled for either. Table 8.4 summarizes read cycle state information. Table 8.4 Read Cycle States ...
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Bit 0—Reserved: This bit is always read as 1. The write value should always be 1. 8.2.3 Wait State Control Register 2 (WCR2) Wait state control register 16-bit read/write register that controls the number of states for ...
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Section 8 Bus State Controller (BSC) Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space) WAIT WAIT Pin Input WAIT WAIT Bits 15–8: DRW7–DRW0 Signal 0 Not sampled during single-mode DMA memory read cycle * 1 Sampled during ...
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Table 8.6 Single-Mode DMA Memory Write Cycle States (External Memory Space) WAIT WAIT Pin Input WAIT WAIT Bits 15–8: DWW7–DWW0 Signal 0 Not sampled during single-mode DMA memory write cycle * 1 Sampled during single-mode DMA memory write cycle (Initial ...
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Section 8 Bus State Controller (BSC) Bits 14 and 13—Long Wait Insertion in Areas 0 and 2, Bits 1, 0 (A02LW1 and A02LW0): A02LW1 and A02LW0 select the long wait states to be inserted (1–4 states) when accessing external memory ...
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DRAM Area Control Register (DCR) The DRAM area control register (DCR 16-bit read/write register that selects the type of DRAM control signal, the number of precharge cycles, the burst operation mode, and the use of address multiplexing. ...
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Section 8 Bus State Controller (BSC) Bit 13—RAS Precharge Cycle Count (TPC): TPC selects whether the RAS signal precharge cycle (T ) will be 1 state or 2. When TPC is cleared 1-state precharge cycle is inserted; ...
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Bits 9 and 8—Multiplex Shift Count 1 and 0 (MXC1 and MXC0): Shift row addresses downward by a certain number of bits (8–10) when row and column addresses are multiplexed (MXE = 1). Regardless of the MXE bit setting, these ...
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Section 8 Bus State Controller (BSC) Bit 7—Refresh Control (RFSHE): RFSHE determines whether or not to perform DRAM refresh operations. When this bit is cleared DRAM refresh control is performed and the refresh timer counter (RTCNT) can ...
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Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR 16-bit read/write register that selects the clock input to the refresh timer counter (RTCNT) and controls compare match interrupts (CMI initialized to H'0000 by ...
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Section 8 Bus State Controller (BSC) Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the compare match interrupt (CMI) generated when CMF is set RTCSR (RTCNT value = RTCOR value). When cleared to 0, the CMI ...
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To prevent RTCSR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'69 is written in the upper byte, and the actual data is written in the ...
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Section 8 Bus State Controller (BSC) Bit 7 Initial value 1 Read/Write R/W 8.2.10 Parity Control Register (PCR) The parity control register (PCR 16-bit read/write register that selects the parity polarity and space to be parity checked. PCR ...
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Bit 14—Parity Output Force (PFRC): PFRC selects whether to produce a forced parity output for testing the parity error check function. When cleared to 0, there is no forced output; when set produces a forced high-level output ...
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Section 8 Bus State Controller (BSC) 8.2.11 Notes on Register Access RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write. Data requires a password when it is written. This prevents data from being mistakenly ...
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Address Space Subdivision 8.3.1 Address Spaces and Areas Figure 8.3 shows the address format used in this chip. A31–A28 A27 A26–A24 Basic bus width selection: Not output externally, but used for basic bus width selection When 0, (H'0000000–H'7FFFFFF), the ...
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Section 8 Bus State Controller (BSC) Table 8.7 How Space is Divided Area Address 0 H'0000000–H'0FFFFFF 1 H'1000000–H'1FFFFFF 2 H'2000000–H'2FFFFFF 3 H'3000000–H'3FFFFFF 4 H'4000000–H'4FFFFFF 5 H'5000000–H'5FFFFFF 6 H'6000000–H'6FFFFFF 7 H'7000000–H'7FFFFFF 0 H'8000000–H'8FFFFFF 1 H'9000000–H'9FFFFFF 2 H'A000000–H'AFFFFFF 3 H'B000000–H'BFFFFFF 4 H'C000000–H'CFFFFFF ...
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As table 8.7 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral chips ...
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Section 8 Bus State Controller (BSC) Table 8.8 A26–A24 Bits and Chip Select Signals Address A26 A25 A24 The chip select signal is output only for ...
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Logical address space H'B000000 H'3000000 H'B3FFFFF (A23, A22 = 00) H'B400000 H'33FFFFF H'3400000 H'B7FFFFF (A23, A22 = 01) H'B800000 H'37FFFFF H'3800000 H'BBFFFFF (A23, A22 = 10) H'BC00000 H'3BFFFFF H'3C00000 H'BFFFFFF (A23, A22 = 11) H'3FFFFFF 16-bit space a. Shadow allocation ...
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Section 8 Bus State Controller (BSC) 8.3.5 Area Descriptions Area 0: Area area with address bits A26–A24 set to 000 and an address range of H'0000000–H'0FFFFFF and H'8000000–H'8FFFFFF. Figure 8.5 shows a memory map of area 0. ...
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Logical address space H'8000000 H'800FFFF H'0000000 H'8010000 Shadow H'000FFFF Shadow H'0010000 Shadow H'8FF0000 Shadow H'8FFFFFF Shadow H'0FF0000 Shadow H'0FFFFFF 32-bit space 32-bit space MD2–MD0 = 010 Note: The bus width of area 0 is determined by the MD2-MD0 pins regardless ...
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Section 8 Bus State Controller (BSC) address bit A27 is 0 and 16 bits when A27 is 1. When the multiplex enable bit (MXE) in the DRAM control register (DCR) is set use the address multiplex function, ...
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Areas 2–4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when A23 and A22 bits are not output and the shadow is in ...
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Section 8 Bus State Controller (BSC) Area 5: Area area with address bits A26–A24 set to 101 and an address range of H'5000000–H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8.8 shows a memory map of area 5. Area 5 is ...
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Area 6: Area area with address bits A26–A24 set to 110 and an address range of H'6000000–H'6FFFFFF and H'E000000–H'EFFFFFF. Figure 8.9 shows a memory map of area 6. In area 6, a space for which address bit ...
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Section 8 Bus State Controller (BSC) Area 7: Area area with address bits A26–A24 set to 111 and an address range of H'7000000–H'7FFFFFF and H'F000000–H'FFFFFFF. Figure 8.10 shows a memory map of area 7. Area 7 is ...
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Accessing External Memory Space In external memory space, a strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: Area 0 (when MD2–MD0 are 000 or ...
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Section 8 Bus State Controller (BSC) CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing) High-level duties of 35% and 50% can be selected for the RD ...
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Wait State Control The number of external memory space access states and the insertion of wait states can be controlled using the WCR1–WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC ...
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Section 8 Bus State Controller (BSC) CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.13 Wait State Timing for External Memory Space Access (2 States Plus Wait Areas 0, 2, and 6 have long wait functions. ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.14 Wait State Timing for External Memory Space Access (1 State Plus Long Wait State (When Set to Insert 3 States) Plus Wait States from WAIT For CPU ...
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Section 8 Bus State Controller (BSC) 8.4.3 Byte Access Control The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte ...
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DRAM Interface Operation When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this chip to DRAMs. 8.5.1 DRAM Address ...
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Section 8 Bus State Controller (BSC) Table 8.10 Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing 8-Bit Shift Output Output Row Column Output Pin Address Address A21 Undefined A21 A20 Value A20 A19 A19 A18 A18 A17 ...
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For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23–A8 address bit values are output to pins A15–A0 the row address. The values for A21–A16 are undefined. The values of bits address ...
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Section 8 Bus State Controller (BSC) CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.17 Short Pitch Access Timing Rev. 7.00 Jan 31, 2006 page 148 of 658 REJ09B0272-0700 Row address ...
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CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may ...
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Section 8 Bus State Controller (BSC A21–A0 RAS CAS Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT states inserted into the DRAM access cycle can be controlled by setting ...
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Regardless of the state of the WAIT signal, when the RW1 bit, the number of wait states selected by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR) are inserted into the ...
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Section 8 Bus State Controller (BSC) CK A21–A0 RAS CASH Byte control CASL WRH WRL CK A21–A0 RAS CASH CASL WRH Byte control WRL Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Pitch) Rev. ...
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DRAM Burst Mode In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously ...
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Section 8 Bus State Controller (BSC) Short-Pitch, High-Speed Page Mode and Long-Pitch High-Speed Page Mode: When burst operation is selected by setting the BE bit DCR, short pitch high-speed page mode or long pitch high-speed page mode ...
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Access A21– A0 Row address RAS CAS WR AD15– AD0 Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.24 Short-Pitch, High-Speed Page Mode ...
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Section 8 Bus State Controller (BSC) The high-level duty of the CAS signal can be selected in short-pitch, high-speed page mode using the CAS duty bit (CDTY) in DCR. When the CDTY bit is cleared to 0, the high-level duty ...
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DRAM area. When the row address for the next DRAM access is the same as the previous DRAM access, burst operation continues. Figure 8.27 shows the timing of RAS down mode when external memory space is accessed ...
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Section 8 Bus State Controller (BSC) RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a DRAM access pauses for access to another space. Burst operation continues only while DRAM access ...
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RTCNT is simultaneously cleared to H'00 and incrementing begins again. When the clock is selected with the CKS2–CKS0 bits, RTCNT immediately begins to increment from its current value. This means that when the RTCOR ...
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Section 8 Bus State Controller (BSC) Self-Refresh Mode: Some DRAMs have a self-refresh mode (battery back-up mode). This is a type of a standby mode in which the refresh timing and refresh addresses are generated inside the DRAM chip. When ...
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Table 8.11 Refresh and Bus Cycle Contention External Memory Space, Multiplexed I/O Space Type of Read Write Refresh Cycle Cycle CAS-before- Yes No RAS refresh Self-refresh Yes Yes Yes: Can be executed in parallel No: Cannot be executed in parallel ...
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Section 8 Bus State Controller (BSC) 8.6 Address/Data Multiplexed I/O Space Access The BSC is equipped with a function that multiplexes address and data input/output on pins AD15–AD0 in area 6. This allows the SH microprocessor to be directly connected ...
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A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the state, lengthening the ...
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Section 8 Bus State Controller (BSC) 8.6.3 Byte Access Control The byte access control signals when the address/data multiplexed I/O space is being accessed are of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access ...
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Warp Mode In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently and in parallel. Warp mode is entered by ...
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Section 8 Bus State Controller (BSC) CK A21– A0 CSn External space write WR AD15– AD0 External space Internal address Internal On-chip write supporting strobe module write Internal data bus Internal On-chip read supporting strobe module read Internal data bus ...
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Table 8.12 Bus Cycle States when Accessing Address Spaces Address Space External memory (areas 1, 3– state fixed; WAIT signal External memory (Areas long wait avail-able) DRAM space (area 1) Multiplexed I/O space (area 6) ...
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Section 8 Bus State Controller (BSC) For details on bus cycles when external spaces are accessed, see section 8.4, Accessing External Memory Space, section 8.5, DRAM Interface Operation, and section 8.6, Address/Data Multiplexed I/O Space Access. Accesses to on-chip spaces ...
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Bus Arbitration The SuperH microcomputer can release the bus to external devices when they request the bus. It has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these two are as follows. ...
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Section 8 Bus State Controller (BSC) 8.10.1 Operation of Bus Arbitration If there is conflict between bus arbitration and refreshing, the operation is as follows DRAM refreshing is requested in this chip when the bus is released and ...
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If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level. BREQ BACK Refresh request Note: * For details see section 8.11.3, Maximum Number of ...
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Section 8 Bus State Controller (BSC) For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike above 2.0 V. Note that delay of the BACK signal increases in units of approximately 0.1 ns/pF. (When ...