HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet

IC SH MPU ROMLESS 240QFN

HD6417727F160CV

Manufacturer Part Number
HD6417727F160CV
Description
IC SH MPU ROMLESS 240QFN
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
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Related parts for HD6417727F160CV

HD6417727F160CV Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7727 Group 32 Hardware Manual Renesas 32-Bit ...

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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

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Rev.6.00 Mar. 27, 2009 Page iv of lvi REJ09B0254-0600 ...

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The SH7727 microprocessor incorporates the 32-bit SH-3 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7727 is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), ...

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User manuals for SH7727 Name of Document SH7727 Hardware Manual SH-3, SH-3E, SH3-DSP Software Manual • User manuals for development tools Name of Document SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User’s Manual SuperH™ ...

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Revisions and Additions Page Previous Version 3, 17, Crystal oscillator, (a) crystal oscillation, 236, oscillator 260, 261, 262, 265, 277, 479, 933 9 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement (PRQP0240KC-B) RAS3/PTJ[0] 129 128 CKE/PTK[5] 127 PTE[1]/USB2_pwr_en 126 PTE[2]/USB1_pwr_en RTS2/USB1d_TXENL ...

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Page Previous Version 323 12.3.2 Description of Areas Area 2: When synchronous DRAM is connected, the RAS3 signal, CAS signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RAS3, CAS, ...

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Page Previous Version 341 Figure 12.17 Basic Timing for Synchronous DRAM Single Write RAS3 343 Figure 12.19 Synchronous DRAM Auto- Refresh Timing RAS3 344 Figure 12.20 Synchronous DRAM Self- Refresh Timing RAS3 346 Figure 12.21 Synchronous DRAM Mode Write Timing ...

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Page Previous Version 543 18.1 Overview As an additional serial communications interface function (SCI card (smart card) interface that is compatible to the ISO/IEC standard 7816-3 for identification of cards is supported. ... ⎯ Section 19 Serial Communication ...

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Page Previous Version 641 20.3.7 Procedures for Transmit or Receive (1) Transmitting in Master Figure 20.9 Example of Transmit Operation in Master No. Time chart Start Settting of SIMDR register, 1 SIMCR register, SITDAR register, SIRDAR register, SICDAR register, SIFCTR ...

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Page Previous Version 681 22.1.2 Pin Configuration Table 22.2 Pin Configuration (Analog Transceiver Signal) USB1P, USB1M, USB2P, USB2M Note: The pins shown in table 22.2 can be used as two-port USB host controller pins one-port USB host controller ...

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Page Previous Version 759 24.5.1 Restriction of the Data Size in IN Transfer When a data packet shorter than MAXPACKETSIZE (short packet) is transferred in the IN data transfer other than the isochronous transfer, following usages are restricted. 2. …Be ...

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Page Previous Version 898 30.2.3 Area 6 Card Status Change Register (PCC0CSCR) Bit 4—PCC0 Status Change (P0SC): Indicates a change in the value of the STSCHG pin of the PC card when the PC card connected to area 6 is ...

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Page Previous Version 985 32.3.12 USB Module Signal Timing Table 32.15 USB Module Signal Timing Item Symbol UCLK external input clock t FREQ frequency (48 MHz) Clock rise time t R48 Clock fall time t F48 989 32.3.14 AC Characteristics ...

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Page Previous Version 1008, Table A.5 Pin Status (Burst ROM/Little 1009 Endian) RAS3 1010, Table A.6 Pin Status (Burst ROM/Big 1011 Endian) RAS3L RAS3 1012 Table A.7 Pin Status (Synchronous DRAM/Little Endian) RAS3 1013 Table A.8 Pin Status (Synchronous DRAM/Big ...

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Section 1 Overview and Pin Functions 1.1 Features............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 11 Section 2 CPU ...................................................................................................................... 21 2.1 Registers............................................................................................................................ 21 2.1.1 General Purpose Registers ................................................................................... 25 2.1.2 Control ...

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Configuration of the TLB .................................................................................... 105 3.3.2 TLB Indexing....................................................................................................... 107 3.3.3 TLB Address Comparison ................................................................................... 108 3.3.4 Page Management Information............................................................................ 110 3.4 MMU Functions................................................................................................................ 111 3.4.1 MMU Hardware Management ............................................................................. 111 3.4.2 MMU Software Management .............................................................................. 111 3.4.3 MMU ...

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General Exceptions .............................................................................................. 141 4.5.3 Interrupts.............................................................................................................. 146 4.6 Usage Notes ...................................................................................................................... 147 Section 5 Cache .................................................................................................................... 149 5.1 Overview........................................................................................................................... 149 5.1.1 Features................................................................................................................ 149 5.1.2 Cache Structure.................................................................................................... 149 5.1.3 Register Configuration......................................................................................... 151 5.2 Register Description.......................................................................................................... 151 5.2.1 Cache Control Register ...

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IRQ Interrupt........................................................................................................ 169 7.2.3 IRL Interrupts ...................................................................................................... 170 7.2.4 PINT Interrupt...................................................................................................... 172 7.2.5 On-Chip Supporting Module Interrupts ............................................................... 172 7.2.6 Interrupt Exception Handling and Priority........................................................... 173 7.3 INTC Registers ................................................................................................................. 179 7.3.1 Interrupt Priority Registers (IPRA ...

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Break ASID Register B (BASRB) ....................................................................... 221 8.3 Operation Description ....................................................................................................... 222 8.3.1 Flow of the User Break Operation ....................................................................... 222 8.3.2 Break on Instruction Fetch Cycle......................................................................... 222 8.3.3 Break by Data Access Cycle................................................................................ 223 8.3.4 Break on X/Y-Memory ...

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Section 10 On-Chip Oscillation Circuits 10.1 Overview........................................................................................................................... 257 10.1.1 Features................................................................................................................ 257 10.2 Overview of the CPG........................................................................................................ 259 10.2.1 CPG Block Diagram ............................................................................................ 259 10.2.2 CPG Pin Configuration ........................................................................................ 261 10.2.3 CPG Register Configuration ................................................................................ 261 10.3 Clock Operating Modes .................................................................................................... ...

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Section 12 Bus State Controller (BSC) 12.1 Overview........................................................................................................................... 283 12.1.1 Features................................................................................................................ 283 12.1.2 Block Diagram..................................................................................................... 285 12.1.3 Pin Configuration................................................................................................. 286 12.1.4 Register Configuration......................................................................................... 287 12.1.5 Area Overview..................................................................................................... 288 12.1.6 PC Card Support .................................................................................................. 292 12.2 BSC Registers ................................................................................................................... 293 12.2.1 ...

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LBSC Operation................................................................................................................ 376 13.2.1 Bus Sharing Architecture ..................................................................................... 376 13.2.2 Usable System Memory ....................................................................................... 376 13.2.3 Bus Arbitration .................................................................................................... 376 13.2.4 LCDC Li Bus Access........................................................................................... 376 13.2.5 USBH Li Bus Access........................................................................................... 377 13.2.6 Setting of DMA Transfer with Bus ...

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Section 15 Timer (TMU) 15.1 Overview........................................................................................................................... 443 15.1.1 Features................................................................................................................ 443 15.1.2 Block Diagram..................................................................................................... 444 15.1.3 Register Configuration......................................................................................... 445 15.2 TMU Registers.................................................................................................................. 446 15.2.1 Timer Start Register (TSTR)................................................................................ 446 15.2.2 Timer Control Register (TCR)............................................................................. 447 15.2.3 Timer Constant Register (TCOR) ........................................................................ ...

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Month Alarm Register (RMONAR) .................................................................... 468 16.2.15 RTC Control Register 1 (RCR1).......................................................................... 469 16.2.16 RTC Control Register 2 (RCR2).......................................................................... 470 16.3 RTC Operation.................................................................................................................. 473 16.3.1 Initial Settings of Registers after Power-On ........................................................ 473 16.3.2 Setting the Time................................................................................................... 473 16.3.3 ...

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Block Diagram..................................................................................................... 544 18.1.3 Pin Configuration................................................................................................. 545 18.1.4 Register Configuration......................................................................................... 545 18.2 Register Descriptions ........................................................................................................ 546 18.2.1 Smart Card Mode Register (SCSCMR) ............................................................... 546 18.2.2 Serial Status Register (SCSSR)............................................................................ 547 18.3 Operation........................................................................................................................... 548 18.3.1 Overview.............................................................................................................. 548 18.3.2 Pin Connections ...

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Section 20 Serial IO (SIOF) 20.1 Overview........................................................................................................................... 605 20.1.1 Features................................................................................................................ 605 20.1.2 Block Diagram..................................................................................................... 606 20.1.3 Terminal............................................................................................................... 607 20.1.4 Register Configuration......................................................................................... 607 20.2 Register Description.......................................................................................................... 608 20.2.1 Mode Register (SIMDR)...................................................................................... 608 20.2.2 Clock Select Register (SISCR) ............................................................................ 610 20.2.3 Transmit ...

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Make Ratio Count Register (MRCR)................................................................... 663 21.2.3 Minimum Pause Count Register (MPCR)............................................................ 663 21.2.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)............................................... 664 21.2.5 Dial Pulse Number Queue (DPNQ) ..................................................................... 669 21.2.6 Ringing Pulse Counter (RCNT)........................................................................... 670 21.2.7 AFE ...

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USB Interrupt Flag Register 1 (USBIFR1).......................................................... 697 23.5.9 USB Trigger Register (USBTRG) ....................................................................... 698 23.5.10 USBFIFO Clear Register (USBFCLR)................................................................ 699 23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) ....................................... 699 23.5.12 USB Data Status Register (USBDASTS) ............................................................ 700 23.5.13 USB ...

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HcControl............................................................................................................. 729 24.2.3 HcCommandStatus .............................................................................................. 732 24.2.4 HcInterruptStatus ................................................................................................. 735 24.2.5 HcInterruptEnable................................................................................................ 737 24.2.6 HcInterruptDisable............................................................................................... 739 24.2.7 HcHCCA.............................................................................................................. 740 24.2.8 HcPeriodCurrentED............................................................................................. 740 24.2.9 HcControlHeadED............................................................................................... 741 24.2.10 HcControlCurrentED ........................................................................................... 741 24.2.11 HcBulkHeadED ................................................................................................... 741 24.2.12 HcBulkCurrentED................................................................................................ 742 24.2.13 HcDoneHead........................................................................................................ 742 ...

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Register Descriptions ........................................................................................................ 767 25.2.1 LCDC Input Clock Register (LDICKR) .............................................................. 767 25.2.2 LCDC Module Type Register (LDMTR) ............................................................ 768 25.2.3 LCDC Data Format Register (LDDFR)............................................................... 771 25.2.4 LCDC Scan Mode Register (LDSMR) ................................................................ 773 25.2.5 LCDC Start Address ...

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Port F Control Register (PFCR)........................................................................... 832 26.3.7 Port G Control Register (PGCR) ......................................................................... 833 26.3.8 Port H Control Register (PHCR) ......................................................................... 835 26.3.9 Port J Control Register (PJCR) ............................................................................ 836 26.3.10 Port K Control Register (PKCR) ......................................................................... 837 26.3.11 ...

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Multi Mode (MULTI = 1, SCN = 0).................................................................... 869 28.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 871 28.4.4 Input Sampling and A/D Conversion Time ......................................................... 873 28.4.5 External Trigger Input Timing............................................................................. 874 28.5 Interrupts ........................................................................................................................... 875 ...

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Pin Description .................................................................................................... 915 31.2.2 Block Diagram..................................................................................................... 916 31.3 Register Descriptions ........................................................................................................ 916 31.3.1 Bypass Register (SDBPR) ................................................................................... 917 31.3.2 Instruction Register (SDIR) ................................................................................. 917 31.3.3 Boundary-Scan Register (SDBSR) ...................................................................... 918 31.4 H-UDI Operations............................................................................................................. 925 31.4.1 TAP Controller .................................................................................................... ...

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A.3 Pin Status when Accessing Address Spaces ................................................................... 1004 Appendix B Control Registers B.1 Register Address Map..................................................................................................... 1019 Appendix C Product Lineup Appendix D Package Dimensions Appendix E Using Versions Previous to the SH7727C E.1 Determining the Version Number Based ...

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Section 1 Overview and Pin Functions Figure 1.1 Block Diagram ....................................................................................................... Figure 1.2 Pin Arrangement (PRQP0240KC-B) ..................................................................... Figure 1.3 Pin Arrangement (PLBG0240JA-A) ...................................................................... 10 Section 2 CPU Figure 2.1 Register Configuration in Each Processing Mode (1) ............................................ 23 Figure 2.2 ...

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Figure 3.14 MMU Exception in Repeat Loop ........................................................................... 123 Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access .......................... 126 Section 4 Exception Handling Figure 4.1 Vector Table........................................................................................................... 132 Figure 4.2 Example of Acceptance Order of General Exceptions ........................................... ...

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Figure 9.11 Hardware Standby Mode Timing (CA = Low during WDT Operation while Standby Mode is Cleared) ............................................................................ 256 Section 10 On-Chip Oscillation Circuits Figure 10.1 Block Diagram of Clock Pulse Generator .............................................................. 259 Figure 10.2 Block Diagram of the ...

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Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access ........................ 355 Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access ......................... 356 Figure 12.29 PCMCIA Space Assignment .................................................................................. 357 Figure 12.30 Basic Timing for PCMCIA I/O ...

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Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access 4 Cycles)................................................................................................................. 422 Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)... 423 Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ...

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Figure 17.7 Sample SCI Initialization Flowchart ...................................................................... 514 Figure 17.8 Sample Serial Transmission Flowchart .................................................................. 515 Figure 17.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 517 Figure 17.10 Sample Serial ...

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Figure 19.2 SCPT[4]/TxD2 Pin................................................................................................. 567 Figure 19.3 SCPT[4]/RxD2 Pin................................................................................................. 568 Figure 19.4 Sample SCIF Initialization Flowchart .................................................................... 592 Figure 19.5 Sample Serial Transmission Flowchart .................................................................. 593 Figure 19.6 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) ...

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Figure 21.6 AFE Control Sequence........................................................................................... 674 Figure 21.7 DAA Block Diagram.............................................................................................. 675 Figure 21.8 Ringing Detect Sequence ....................................................................................... 676 Section 22 USB Pin Multiplex Controller Figure 22.1 Block Diagram of USB PIN Multiplexer ............................................................... 680 Figure 22.2 Example 1 of ...

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Figure 25.5 Power-Supply Control Sequence and States of the LCD Module .......................... 803 Figure 25.6 Power-Supply Control Sequence and States of the LCD Module .......................... 804 Figure 25.7 Power-Supply Control Sequence and States of the LCD Module .......................... 804 Figure ...

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Figure 30.2 Continuous 32-MB Area Mode .............................................................................. 889 Figure 30.3 Continuous 16-MB Area Mode (Area 6)................................................................ 890 Figure 30.4 SH7727 Interface.................................................................................................... 903 Figure 30.5 PCMCIA Memory Card Interface Basic Timing ................................................... 907 Figure 30.6 PCMCIA Memory Card Interface Wait Timing..................................................... ...

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Figure 32.26 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 1, CAS Latency = 3, TPC = 0) ................................................................... 960 Figure 32.27 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = ...

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Figure 32.60 Output Load Circuit ............................................................................................... 989 Figure 32.61 Load Capacitance vs. Delay Time.......................................................................... 990 Appendix D Package Dimensions Figure D.1 Package Dimensions (PRQP0240KC-B).............................................................. 1031 Figure D.2 Package Dimensions (PLBG0240JA-A) .............................................................. 1032 Rev.6.00 Mar. 27, 2009 Page xlviii of lvi ...

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Section 1 Overview and Pin Functions Table 1.1 SH7727 Features .................................................................................................... Table 1.2 SH7727 Pin Function ............................................................................................. 11 Section 2 CPU Table 2.1 Initial Register Values ............................................................................................ 24 Table 2.2 Detail Behavior Under Each SH3-DSP Mode........................................................ 33 Table 2.3 Destination ...

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Section 3 Memory Management Unit (MMU) Table 3.1 Register Configuration ........................................................................................... 103 Table 3.2 Access States Designated and PR Bits..................................................... 110 Section 4 Exception Handling Table 4.1 Register Configuration ........................................................................................... 131 Table 4.2 Exception Event Vectors ........................................................................................ ...

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Section 10 On-Chip Oscillation Circuits Table 10.1 Clock Pulse Generator Pins and Functions............................................................. 261 Table 10.2 Register Configuration ........................................................................................... 261 Table 10.3 Clock Operating Modes.......................................................................................... 262 Table 10.4 Available Combination of Clock Mode and FRQCR Values................................. 264 Table 10.5 Register ...

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Table 14.9 DMAC Sate after the Fourth Transfer Ends........................................................... 439 Table 14.10 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter .............................................................................. 440 Section 15 Timer (TMU) Table 15.1 TMU Register Configuration ................................................................................. 445 Table 15.2 ...

Page 55

Table 18.3 Register Settings for the Smart Card Interface ....................................................... 551 Table 18.4 Relationship CKS1 and CKS0 .................................................................... 553 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0).................................. 553 Table 18.5 Examples of SCBRR ...

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Section 22 USB Pin Multiplex Controller Table 22.1 Pin Configuration (Digital Transceiver Signal)...................................................... 681 Table 22.2 Pin Configuration (Analog Transceiver Signal) ..................................................... 681 Table 22.3 Pin Configuration (Power Control signal).............................................................. 682 Table 22.4 Register Configuration ........................................................................................... 682 Section 23 USB ...

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Section 28 A/D Converter Table 28.1 A/D Converter Pins ................................................................................................ 859 Table 28.2 A/D Converter Registers ........................................................................................ 860 Table 28.3 Analog Input Channels and A/D Data Registers .................................................... 861 Table 28.4 A/D Conversion Time (Single Mode) .................................................................... 874 Table 28.5 ...

Page 58

Table 32.16 USB Electrical Characteristics (Full-Speed) .......................................................... 986 Table 32.17 USB Electrical Characteristics (Low-Speed) ......................................................... 986 Table 32.18 AFEIF Module Signal Timing ............................................................................... 987 Table 32.19 A/D Converter Characteristics ............................................................................... 991 Table 32.20 D/A Converter Characteristics ............................................................................... 991 Appendix A ...

Page 59

Section 1 Overview and Pin Functions 1.1 Features The SH7727 is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH RISC engine architecture CPU with digital signal processing (DSP) extension as its core that has a cache memory, an ...

Page 60

Section 1 Overview and Pin Functions Table 1.1 SH7727 Features Item Features • CPU Original Renesas SuperH architecture • Object code level compatible with SH-1, SH-2 and SH-3 • 32-bit internal data bus • General-register ⎯ Sixteen 32-bit general registers ...

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Item Features • DSP Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data bus • Multiplier, ALU, barrel shifter and DSP register • 16 bits x 16 bits → 32-bit one cycle multiplier • Large DSP data register ⎯ ...

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Section 1 Overview and Pin Functions Item Features • Memory 4 Gbytes of address space, 256 address spaces (ASID 8 bits) management • Page unit sharing unit (MMU) • Supports multiple page sizes: 1 kbytes or 4 kbytes • 128-entry, ...

Page 63

Item Features • Bus state Physical address space divided into six areas (area 0, areas 2 to 6), each of controller (BSC Mbytes, with the following features settable for each area: ⎯ Bus size (8, 16, or ...

Page 64

Section 1 Overview and Pin Functions Item Features Serial I/O (SIOF) • Synchronous 16 step, 8/16/32 bit word FIFO for transmission/reception • Supports 8-bit/16-bit mono/stereo sound playback or recording • DMA can be transferred • Supports frame sync signal • ...

Page 65

Item Features • LCD controller From 1024 x 1024 pixels can be supported (LCDC) • 4/8/15/16 bpp (bit per pixel) color modes • 1/2/4/6 bpp (bit per pixel) gray scale • 8-bit Frame rate controller • ...

Page 66

Section 1 Overview and Pin Functions 1.2 Block Diagram Internal SRAM (XY RAM) SuperH instruction/data CPU core for CPU/DSP 16 kbytes Cache access controller controller (CCN) Bus state controller Internal bus (I bus) (BSC) Real time clock smart card (RTC) ...

Page 67

Pin Description 1.3.1 Pin Arrangement LCD15/PTM[3]/PINT[10] 181 LCD14/PTM[2]/PINT[9] 182 LCD13/PTM[1]/PINT[8] 183 LCD12/PTM[0] 184 STATUS0/PTJ[6] 185 Vcc = 1.9 V, Vss = GND for CPU core STATUS1/PTJ[7] 186 CL2/PTH[7] 187 VccQ = 3.3 V, VssQ = GND for I/O buffer ...

Page 68

Section 1 Overview and Pin Functions Vcc- EXT A MD1 NMI IRQ1 RTC AL2 AN6 AVss Vss- B XTAL2 MD2 RTC AVcc_ C AN5 AVcc IRQ0 IRQ3 MD5 CKIO2 D29 USB AN3 AN7 AN2 IRQ2 IRQ4 ...

Page 69

Pin Functions Table 1.2 SH7727 Pin Function Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name ...

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Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name A10 30 D10 31 C10 32 B10 33 C11 34 D11 35 B11 36 A11 37 D12 38 C12 39 B12 40 A12 41 ...

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Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 61 A19 62 D18 63 B19 64 C18 65 C19 66 E18 67 D19 68 D17 69 E19 70 D16 71 E17 72 E16 73 F19 74 F18 75 F17 76 F16 77 ...

Page 72

Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 94 L16 95 L18 96 L19 97 M16 98 M17 99 M18 100 M19 101 N16 102 N17 103 N18 104 N19 105 P16 106 P17 107 ...

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Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 118 V19 119 T18 120 V18 121 W19 122 V16 123 W18 124 V17 125 W17 126 V15 127 W16 128 U16 129 W15 130 T16 131 U15 132 T15 133 W14 134 ...

Page 74

Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 142 V12 143 U12 144 T12 145 W11 146 V11 147 T11 148 U11 149 W10 150 T10 151 U10 152 V10 153 U9 154 T9 155 ...

Page 75

Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 167 V6 168 W6 169 T5 170 U5 171 U3 172 W5 173 U4 174 W4 175 V5 176 W3 177 V3 178 W2 179 V4 180 V2 181 W1 182 T2 183 ...

Page 76

Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 196 P4 197 N1 198 N2 199 N3 200 N4 201 M1 202 M2 203 M3 204 M4 205 L1 206 L2 207 L4 208 L3 209 ...

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Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 226 F3 227 F2 228 F1 229 E4 230 E3 231 C3 232 E1 233 D3 234 D1 235 E2 236 C1 237 C2 238 B1 239 D2 240 B2 Notes: All Vcc/Vss ...

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Section 1 Overview and Pin Functions Rev.6.00 Mar. 27, 2009 Page 20 of 1036 REJ09B0254-0600 ...

Page 79

Registers The SH7727 has the same registers as in SH-3. In addition, the SH7727 also support the same DSP-related registers seen in SH-DSP. The basic software-accessible registers are divided into four distinct groups: • General-purpose registers • Control registers ...

Page 80

Section 2 CPU • PC: Program counter This section explains the usage of these registers in different modes. Figures 2.1 and 2.2 show the register configuration in each processing mode. Switching between user mode and privileged mode is carried out ...

Page 81

R0_BANK0 *2 R1_BANK0 *2 R2_BANK0 *2 R3_BANK0 *2 R4_BANK0 *2 R5_BANK0 *2 R6_BANK0 *2 R7_BANK0 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC (a) User mode register configuration Notes: 1. The ...

Page 82

Section 2 CPU (d) DSP mode register configuration (DSP = 1) Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers General registers R0 ...

Page 83

General Purpose Registers There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions used as an index register. With a ...

Page 84

Section 2 CPU On the other hand registers are also used for the DSP data address calculations, see figure 2.4, when DSP extension is enabled. Another symbol that represents the purpose of the registers in DSP type ...

Page 85

The name Ix is the alias for R8. Other aliases are as follows. Ax0: .REG (R4) Ax1: .REG (R5) Ix: .REG (R8) Ay0: .REG (R6) Ay1: .REG (R7) Iy: .REG (R9) This is optional. If you need another alias for ...

Page 86

Section 2 CPU three-step instruction. When RF[1:0] = 10, it means the current repeat module consists of four or more instructions. Although RC[11:0] and RF[1:0] can be changed by a store/load to SR, use of the dedicated manipulation instruction SETRC ...

Page 87

0-0 DSP DMY DMX bit: Processor operation mode Privileged mode User mode RB bit: Register bank bit; used ...

Page 88

Section 2 CPU MOD ME ME: Modulo end address, MS: Modulo start address Saved status register (SSR) Stores current SR value at time of exception to indicate processor status when returning to instruction ...

Page 89

System Registers The SH7727 has four system registers, MACL, MACH, PR and PC (figure 2.6). 31 MACH MACL DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. So, data transfer ...

Page 90

Section 2 CPU When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits are automatically cleared. A0 and A1 can be stored to ...

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Table 2.2 Detail Behavior Under Each SH3-DSP Mode Supervisor Mode User Mode & & Fields DSP = 0 DSP = OK illegal L: OK instruction RB S: OK, S, ...

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Section 2 CPU other than A0G and A1G in the word mode, lower half of the register is cleared. When A1, the data is sign-extended to bits and lower half ...

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Table 2.4 Source Register of DSP Operations Registers Instructions A0, A1 DSP Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data MOVX/Y.W, MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 DSP Fixed-point, PDMSB, Y0, Y1 PSHA M0, M1 ...

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Section 2 CPU Table 2.5 DSR Register Bits Bit Name (Abbreviation) 31–8 Reserved bits 7 Signed greater than bit (GT) 6 Zero bit (Z) 5 Negative bit (N) 4 Overflow bit (V) 3–1 Status selection bits (CS) Designate the mode ...

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MOVS.W, MOVS.L 39 A0G A1G DSR 7 Figure 2.8 Connections of DSP Registers and Buses The DSP unit has DSP status register (DSR). The DSR has conditions of the DSP data operation result (zero, negative, and so on) ...

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Section 2 CPU 2.2 Data Format 2.2.1 Data Format in Registers (Non-DSP Type) Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only a byte (8 bits word (16 bits sign-extended ...

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DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer With guard bits Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) DSP type logical CPU type integer Longword ...

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Section 2 CPU 2.2.3 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if the word data starting from an address ...

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Table 2.6 Word Data Sign Extension SH7727 CPU MOV.W @(disp,PC),R1 ADD R1,R0 ........ .DATA.W H'1234 Note: Immediate data is referenced by @(disp,PC). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a ...

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Section 2 CPU Table 2.8 T Bit SH7727 CPU Description If R0 ≥ R1, the T bit is set. CMP/GE R1,R0 BT TRGET0 A branch is made to TRGET0 if R0 ≥ R1 TRGET1 if R0 < R1. ...

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Absolute Addresses: When data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a ...

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Section 2 CPU 2.4 Instruction Formats 2.4.1 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions Addressing ...

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Addressing Instruction Mode Format Register @(disp:4, Rn) Effective address is register Rn contents with indirect with displacement Indexed @(R0, Rn) register indirect GBR indirect @(disp:8, with GBR) displacement Effective Address Calculation Method 4-bit displacement disp added. After disp is zero-extended, ...

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Section 2 CPU Addressing Instruction Mode Format Indexed GBR @(R0, GBR) indirect PC-relative @(disp:8, PC) Effective address is PC with 8-bit displacement with displacement Rev.6.00 Mar. 27, 2009 Page 46 of 1036 REJ09B0254-0600 Effective Address Calculation Method Effective address is ...

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Addressing Instruction Mode Format PC-relative disp:8 disp:12 Rn Immediate #imm:8 #imm:8 #imm:8 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied disp + (sign-extended) × 2 Effective address ...

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Section 2 CPU 2.4.2 DSP Data Addressing Two different memory accesses are made with DSP instructions. The two kinds of instructions are X and Y data transfer instructions (MOVX.W, MOVY.W) and single data transfer instructions (MOVS.W, MOVSL). The data addressing ...

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Addition index register addressing: The Ax and Ay registers are address pointers. After a data transfer, the value of the register is added to each (post-increment). 3. Increment address register addressing: The Ax and Ay registers ...

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Section 2 CPU Single Data Addressing: DSP instructions include two single data transfer instructions (MOVS.W, MOVS.L) that load data into, or store data from, a DSP register. With these instructions, one of registers used as the ...

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Modulo Addressing: Like other DSPs, the SH7727 has a modulo addressing mode. Address registers are updated in the same way in this mode. When the address pointer value reaches the preset modulo end address, the address pointer value becomes the ...

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Section 2 CPU 31 R4[Ax R8[Ix] R5[Ax ALU 15 An example of modulo addressing is given below H'7008; ME=H'700C; R4=H'A5007008; DMX = 1; DMY = result of the above settings, the ...

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DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX), including modulo addressing, are shown below Operation is MOVX.W MOVY ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be ...

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Section 2 CPU /* The value to be added to the address register depends on addressing operations. For example, (+2 or R8[Ix] or +0) means that + operation is increment R8[Ix operation is add-index-reg +0 : ...

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Table 2.14 CPU Instruction Formats Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx m type 15 0 xxxx mmmm xxxx xxxx Source Destination Operand Operand — — — nnnn: register ...

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Section 2 CPU Instruction Format nm type 15 0 xxxx xxxx nnnn mmmm md type 15 0 xxxx xxxx dddd mmmm nd4 type 15 0 dddd xxxx xxxx nnnn nmd type 15 0 xxxx nnnn mmmm dddd Rev.6.00 Mar. 27, ...

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Instruction Format d type 15 0 xxxx xxxx dddd dddd d12 type 15 0 xxxx dddd dddd dddd nd8 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx ...

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Section 2 CPU 2.4.4 DSP Instruction Formats The SH7727 includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel ...

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Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.15, and that of single data transfer instructions in table 2.16. Table 2.15 Double Data Transfer Instruction Formats Type Mnemonic X memory NOPX ...

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Section 2 CPU Table 2.16 Single Data Transfer Instruction Formats Type Mnemonic Single MOVS.W @-As,Ds data MOVS.W @As,Ds transfer MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L ...

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Table 2.17 A-Field Parallel Data Transfer Instructions Section 2 CPU Rev.6.00 Mar. 27, 2009 Page 61 of 1036 REJ09B0254-0600 ...

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Section 2 CPU Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions Rev.6.00 Mar. 27, 2009 Page 62 of 1036 REJ09B0254-0600 ...

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Section 2 CPU Rev.6.00 Mar. 27, 2009 Page 63 of 1036 REJ09B0254-0600 ...

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Section 2 CPU 2.5 Instruction Set 2.5.1 CPU Instruction Set The SH-1/SH-2/SH-3 compatible instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.19. Tables 2.20 to 2.25 show the instruction notation, machine ...

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Table 2.19 CPU Instruction Types Kinds of Type Instruction Op Code Data transfer 5 MOV instructions MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operation ADDC instructions ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU ...

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Section 2 CPU Kinds of Type Instruction Op Code Logic 6 AND operation NOT instructions OR TAS TST XOR Shift 12 ROTL instructions ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD Branch 9 BF instructions BT BRA ...

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Kinds of Type Instruction Op Code System 15 CLRT control CLRMAC instructions CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: 68 Function T bit clear MAC register clear S bit clear Load into control ...

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Section 2 CPU The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Instruction Code Indicated in MSB ↔ Indicated by ...

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Data Transfer Instructions Table 2.20 Data Transfer Instructions Instruction Operation imm → Sign extension MOV #imm,Rn → Rn (disp × PC) → Sign MOV.W @(disp,PC),Rn extension → Rn (disp × PC) → Rn MOV.L @(disp,PC),Rn Rm ...

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Section 2 CPU Instruction Operation Rm → (R0 + Rn) MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) (R0 + Rm) → Sign MOV.B @(R0,Rm),Rn extension → Rn (R0 + Rm) → Sign MOV.W @(R0,Rm),Rn extension → Rn (R0 ...

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Arithmetic Operation Instructions Table 2.21 Arithmetic Operation Instructions Instruction Operation → Rn ADD Rm, imm → Rn ADD #imm, → Rn, ADDC Rm,Rn Carry → → ...

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Section 2 CPU Instruction Operation Unsigned operation of DMULU.L Rm,Rn Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rn – 1 → Rn → T, else 0 → T ...

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Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required when the operation result is read from the MAC register immediately after the instruction. 2. The normal minimum number of execution cycles is one, ...

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Section 2 CPU Shift Instructions Table 2.23 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL Rn LSB → Rn → T ROTR Rn T ← Rn ← T ROTCL Rn T → Rn → T ROTCR Rn Rn ...

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Branch Instructions Table 2.24 Branch Instructions Instruction Operation disp × → PC; BF label nop (where label is disp + PC) Delayed branch BF/S label ...

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Section 2 CPU System Control Instructions Table 2.25 System Control Instructions Instruction Operation 0 → MACH, MACL CLRMAC 0 → S CLRS 0 → T CLRT Rm → SR LDC Rm,SR Rm → GBR LDC Rm,GBR Rm → VBR LDC ...

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Instruction Operation (Rm) → R5_BANK, LDC.L @Rm → Rm R5_BANK (Rm) → R6_BANK, LDC.L @Rm → Rm R6_BANK (Rm) → R7_BANK, LDC.L @Rm → Rm R7_BANK Rm → MACH LDS Rm,MACH ...

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Section 2 CPU Instruction Operation Rn–4 → Rn, SR → (Rn) STC.L SR,@–Rn Rn–4 → Rn, GBR → (Rn) STC.L GBR,@–Rn Rn–4 → Rn, VBR → (Rn) STC.L VBR,@–Rn Rn–4 → Rn, SSR → (Rn) STC.L SSR,@–Rn Rn–4 → Rn, ...

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DSP Extended-Function Instructions 2.6.1 Introduction The newly added instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit 2. DSP unit memory-register single and double data transfer 3. DSP unit parallel processing ...

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Section 2 CPU 2.6.2 Added CPU System Control Instructions The new instructions in this class are treated as part of the CPU core functions, and therefore all the added instructions have a 16-bit code length. All the additional instructions belong ...

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Table 2.26 Added CPU System Control Instructions Instruction Instruction Code SETRC #imm 10000010iiiiiiii SETRC Rn 0100nnnn00010100 LDRS @(disp,PC) 10001100dddddddd LDRE @(disp,PC) 10001110dddddddd STC MOD,Rn 0000nnnn01010010 STC RS,Rn 0000nnnn01100010 STC RE,Rn 0000nnnn01110010 STS DSR,Rn 0000nnnn01101010 STS A0,Rn 0000nnnn01111010 STS X0,Rn 0000nnnn10001010 ...

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Section 2 CPU Instruction Instruction Code LDC.L @Rn+,RE 0100nnnn01110111 LDS Rn,DSR 0100nnnn01101010 LDS Rn,A0 0100nnnn01111010 LDS Rn,X0 0100nnnn10001010 LDS Rn,X1 0100nnnn10011010 LDS Rn,Y0 0100nnnn10101010 LDS Rn,Y1 0100nnnn10111010 LDC Rn,MOD 0100nnnn01011110 LDC Rn,RS 0100nnnn01101110 LDC Rn,RE 0100nnnn01111110 2.6.3 Single and Double ...

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Table 2.27 Double Data Transfer Instructions Instruction X memory NOPX data transfer MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx 111100A*D*0*11** MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix 111100A*D*1*11** Y memory NOPY data transfer MOVY.W @Ay,Dy MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy 111100*A*D*0**11 MOVY.W Da,@Ay ...

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Section 2 CPU Table 2.28 Single Data Transfer Instructions Instruction Instruction Code MOVS.W @-As,Ds 111101AADDDD0000 MOVS.W @As,Ds 111101AADDDD0100 MOVS.W @As+,Ds 111101AADDDD1000 MOVS.W @As+Ix,Ds 111101AADDDD1100 MOVS.W Ds,@-As* 111101AADDDD0001 MOVS.W Ds,@As* 111101AADDDD0101 MOVS.W Ds,@As+* 111101AADDDD1001 MOVS.W Ds,@As+Ix* 111101AADDDD1101 MOVS.L @-As,Ds 111101AADDDD0010 MOVS.L ...

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The correspondence between DSP data transfer operands and registers is shown in table 2.29. CPU core registers are used as a pointer address that indicates a memory address. Table 2.29 Correspondence between DSP Data Transfer Operands and Registers Register Ax ...

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Section 2 CPU basically the same as in the double data transfer instructions described in section 2.6.3, Single and Double Data Transfer for DSP Data Instructions, but has a special function in load instructions. B-field data operation instructions are of ...

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Table 2.31 Correspondence between DSP Instruction Operands and Registers ALU/BPU Operations Register Sx A0 Yes A1 Yes Yes X1 Yes Y0 Y1 When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. ...

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Section 2 CPU Table 2.32 DSP Operation Instructions Instruction Instruction Code PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz DCT PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz DCF PADD Sx,Sy,Dz 111110********** ...

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Instruction Instruction Code DCF PSHA Sx,Sy,Dz 111110********** 10010011xxyyzzzz PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz DCT PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz DCF PSHL Sx,Sy,Dz 111110********** 10000011xxyyzzzz PCOPY Sx,Dz 111110********** 11011001xx00zzzz PCOPY Sy,Dz 111110********** 1111100100yyzzzz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz DCT PCOPY Sy,Dz 111110********** 1111101000yyzzzz ...

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Section 2 CPU Instruction Instruction Code DCT PDMSB Sx,Dz 111110********** 10011110xx00zzzz DCT PDMSB Sy,Dz 111110********** 1011111000yyzzzz DCF PDMSB Sx,Dz 111110********** 10011111xx00zzzz DCF PDMSB Sy,Dz 111110********** 1011111100yyzzzz PINC Sx,Dz 111110********** 10011001xx00zzzz PINC Sy,Dz 111110********** 1011100100yyzzzz DCT PINC Sx,Dz 111110********** 10011010xx00zzzz DCT ...

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Instruction Instruction Code DCT PNEG Sx,Dz 111110********** 11001010xx00zzzz DCT PNEG Sy,Dz 111110********** 1110101000yyzzzz DCF PNEG Sx,Dz 111110********** 11001011xx00zzzz DCF PNEG Sy,Dz 111110********** 1110101100yyzzzz POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz DCT POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz DCF POR Sx,Sy,Dz 111110********** 10110111xxyyzzzz PAND Sx,Sy,Dz 111110********** ...

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Section 2 CPU Instruction Instruction Code DCT PDEC Sx,Dz 111110********** 10001010xx00zzzz DCT PDEC Sy,Dz 111110********** 1010101000yyzzzz DCF PDEC Sx,Dz 111110********** 10001011xx00zzzz DCF PDEC Sy,Dz 111110********** 1010101100yyzzzz PCLR Dz 111110********** 100011010000zzzz DCT PCLR Dz 111110********** 100011100000zzzz DCF PCLR Dz 111110********** 100011110000zzzz ...

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Instruction Instruction Code DCT PSTS MACL,Dz 111110********** 110111100000zzzz DCF PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz DCT PLDS Dz,MACH 111110********** 111011100000zzzz DCF PLDS Dz,MACH 111110********** 111011110000zzzz PLDS Dz,MACL 111110********** 111111010000zzzz DCT PLDS Dz,MACL 111110********** 111111100000zzzz DCF PLDS Dz,MACL 111110********** ...

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Section 2 CPU Table 2.33 DC Bit Update Definitions CS [2:0] Condition Mode Carry or borrow mode Negative value mode Zero value mode Overflow mode ...

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Conditional Operations and Data Transfer: Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for ...

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Section 2 CPU Table 2.34 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVS.W @R4+,X0 NOPX NOPX NOP Rev.6.00 Mar. 27, ...

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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7727 has an on-chip memory management unit (MMU) that implements address translation. The SH7727 features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables ...

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Section 3 Memory Management Unit (MMU) When address translation from virtual memory to physical memory is performed using the MMU, it may occur that the relevant translation information is not recorded in the MMU, with the result that one process ...

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Physical memory Process 1 3.1.3 SH7727 MMU Logical Address Space: The SH7727 uses 32-bit logical addresses to access a 4-Gbyte logical address space that is divided into several areas. Address space mapping is shown in figure 3.2. In the privileged ...

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Section 3 Memory Management Unit (MMU) Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2 area, setting the top three logical address bits (bits 31, 30, and 29 generates the ...

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H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) H'A0000000 0.5-Gbyte fixed physical space, non-cacheable H'C0000000 0.5-Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5-Gbyte control space, non-cacheable H'FFFFFFFF Privileged mode Figure 3.2 Logical Address Space Mapping Physical ...

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Section 3 Memory Management Unit (MMU) address and the page control information are read from the TLB and the physical address is determined. If the logical address is not registered in the TLB, a TLB miss exception occurs and processing ...

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Register Configuration Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration Name Page table entry register high PTEH Page table entry register low Translation table base register TLB exception address register MMU control register ...

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Section 3 Memory Management Unit (MMU) 4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the logical address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. ...

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TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number, the address space identifier, and ...

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Section 3 Memory Management Unit (MMU (15) (2) VPN (31−17) VPN (11−10) ASID Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address ...

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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits and ASID bits PTEH are used as the index number. The index number ...

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Section 3 Memory Management Unit (MMU) Virtual address 31 17 Index 0 VPN(31−17) VPN(11−10) 31 Address array 3.3.3 TLB Address Comparison A TLB address comparison is performed when an instruction is fetched from a program in external memory or data ...

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The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes ( but not when there is sharing (SH = 1). When ...

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Section 3 Memory Management Unit (MMU) 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates ...

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MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the logical address accessed by a process and performs address translation by controlling the TLB in accordance with the ...

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Section 3 Memory Management Unit (MMU) 3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified ...

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MMUCR Index PTEH register VPN VPN Write VPN(31−17) VPN(11−10 Address array Figure 3.9 Operation of LDTLB Instruction 3.4.4 Avoiding Synonym Problems When a 1-kbyte ...

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Section 3 Memory Management Unit (MMU) the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. Note: When multiple address information items use the same ...

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When using a 4-kbyte page Virtual address VPN Physical address PPN When using a 1-kbyte page Virtual address 31 11 VPN Physical address 31 11 PPN Figure 3.10 Synonym Problem Section 3 ...

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Section 3 Memory Management Unit (MMU) 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the logical address and the address ...

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PTEL register in the SH7727 using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the ...

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Section 3 Memory Management Unit (MMU) 3.5.3 TLB Invalid Exception A TLB invalid exception results when the logical address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the ...

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Initial Page Write Exception An initial page write exception results in a write access when the logical address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is ...

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Section 3 Memory Management Unit (MMU) No VPNs match? TLB miss exception PR check 00/01 W R/W? TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.11 MMU Exception Generation Flowchart Rev.6.00 Mar. 27, 2009 Page ...

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Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) MMU Exception in the Instruction Fetch Mode : Exception source stage IF = Instruction fetch ID = Instruction decode EX = Instruction execution MA = Memory ...

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Section 3 Memory Management Unit (MMU) MMU Exception in the Data Access Mode Exception source stage : Stage cancellation for instruction that has begun execution IF = Instruction fetch ID = Instruction decode ...

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MMU Exception in Repeat Loop When MMU exception or CPU address error occurs immediately before or within a repeat loop, the PC of the instruction that generated the exception can not be saved in SPC correctly and repeat loop ...

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Section 3 Memory Management Unit (MMU) ( more instructions repeated (inst1, inst2, ..., instN, SR.RC=2) inst inst0 inst1 inst2 instN-3 ...

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Address Array The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the 32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. The address field specifies information for ...

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Section 3 Memory Management Unit (MMU) (1) TLB Address Array Access Read access 31 Address field 11110010 31 Data field Write access 31 Address field 11110010 31 Data field VPN (2) TLB Data Array Access Read/write access 31 ...

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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 30 ; MMUCR.IX=0 ; VPN(31–17)=B'0001 0101 ...

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Section 3 Memory Management Unit (MMU) 3.7 Usage Notes 1. Instructions that manipulate the bit in register SR (the LDC Rm, SR instruction, LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB ...

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Measures to avoid the problem The following two measures should be taken to avoid the problem described above: a. After performing a reset and before setting MMUCR, initialize to 1 the upper four bits of the ...

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Section 3 Memory Management Unit (MMU) Rev.6.00 Mar. 27, 2009 Page 130 of 1036 REJ09B0254-0600 ...

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Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the ...

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Section 4 Exception Handling contents of the PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The ...

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Table 4.2 Exception Event Vectors Exception Current Type Instruction Exception Event Reset Aborted Power-on reset Manual reset H-UDI reset General Aborted CPU address error exception and retried (instruction access) events TLB miss (instruction access not in repeat loop) TLB miss ...

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Section 4 Exception Handling Exception Current Type Instruction Exception Event General Completed Nonmaskable interrupt 3 interrupt External hardware requests interrupt H-UDI interrupt Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. The ...

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Pipeline Sequence: Instruction Instruction TLB miss (instruction access) Instruction Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and RIE (instruction simultaneous detection Handling Order: ...

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Section 4 Exception Handling All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type ...

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Exception Type General interrupt requests Note: Exception codes H'120, H'140, and H'3E0 are reserved. 4.2.5 Exception Request Masks When the BL bit exceptions and interrupts are accepted general exception event occurs when the BL ...

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Section 4 Exception Handling 4.2.6 Returning from Exception Handling The RTE instruction is used to return from exception handling. When RTE is executed, the SPC value is set in the PC, and the SSR value in SR, and the return ...

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EXPEVT register, INTEVT and INTEVT2 registers Exception code 0: Reserved bits, always read as zero imm: 8-bit immediate data in TRAPA instruction Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers 4.4 Exception Handling ...

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Section 4 Exception Handling 6. Instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (VBR) and H'00000600 to invoke the exception handler. 4.4.3 General Exceptions When the ...

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Manual Reset ⎯ Conditions: RESETM low ⎯ Operations: EXPEVT set to H'020, VBR and SR initialized, branch H'A0000000. Initialization sets the VBR register to H'00000000. In SR, the MD, RB, and BL bits are set to ...

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Section 4 Exception Handling To speed up TLB miss processing, the offset differs from other exceptions. • TLB invalid exception ⎯ Conditions: Comparison of TLB addresses shows address match but ⎯ Operations: The logical address (32 bits) ...

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