HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet
HD6417720BP133BV
Specifications of HD6417720BP133BV
Related parts for HD6417720BP133BV
HD6417720BP133BV Summary of contents
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7720 Group, SH7721 Group 32 User's Manual: ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The SH7720 or SH7721 Group RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...
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Rules: Register name: Bit order: Number notation: Binary is B'xx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions ...
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Abbreviations ADC Analog to Digital Converter ALU Arithmetic Logic Unit ASE Adaptive System Evaluator ASID Address Space Identifier AUD Advanced User Debugger BCD Binary Coded Decimal bps bit per second BSC Bus State Controller CCN Cache memory Controller CMT Compare ...
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ROM Read Only Memory RSA Rivest Shamir Adleman RTC Real Time Clock SCIF Serial Communication Interface with FIFO SDHI SD Host Interface SDRAM Synchronous DRAM SSL Secure Socket Layer TAP Test Access Port T.B Determined TLB Translation Lookaside ...
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Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 Block Diagram.................................................................................................................... 10 1.3 Pin Assignments ................................................................................................................. 10 1.3.1 Pin Assignments ................................................................................................. 10 1.3.2 Pin Functions ...................................................................................................... 25 Section 2 CPU......................................................................................................37 2.1 Processing States and Processing Modes............................................................................ 37 2.1.1 Processing States................................................................................................. 37 2.1.2 ...
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CPU Extended Instructions................................................................................................. 89 3.3.1 DSP Repeat Control............................................................................................ 89 3.4 DSP Data Transfer Instructions ........................................................................................ 100 3.4.1 General Registers.............................................................................................. 104 3.4.2 DSP Data Addressing ....................................................................................... 106 3.4.3 Modulo Addressing........................................................................................... 108 3.4.4 Memory Data Formats ...................................................................................... 110 3.4.5 Instruction Formats ...
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TLB Address Comparison ................................................................................ 179 4.3.4 Page Management Information ......................................................................... 181 4.4 MMU Functions................................................................................................................ 182 4.4.1 MMU Hardware Management .......................................................................... 182 4.4.2 MMU Software Management ........................................................................... 183 4.4.3 MMU Instruction (LDTLB).............................................................................. 183 4.4.4 Avoiding Synonym Problems ........................................................................... 185 4.5 ...
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Section 6 X/Y Memory .....................................................................................213 6.1 Features............................................................................................................................. 213 6.2 Operation .......................................................................................................................... 214 6.2.1 Access from CPU.............................................................................................. 214 6.2.2 Access from DSP .............................................................................................. 214 6.2.3 Access from Bus Master Module...................................................................... 215 6.3 Usage Notes ...................................................................................................................... 215 6.3.1 Page Conflict .................................................................................................... 215 ...
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Interrupt Control Register 0 (ICR0).................................................................. 249 8.3.3 Interrupt Control Register 1 (ICR1).................................................................. 250 8.3.4 Interrupt Request Register 0 (IRR0) ................................................................. 252 8.3.5 Interrupt Request Register 1 (IRR1) ................................................................. 253 8.3.6 Interrupt Request Register 2 (IRR2) ................................................................. 254 8.3.7 Interrupt ...
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Refresh Timer Counter (RTCNT)..................................................................... 329 9.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 330 9.4.8 SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3)...................................... 330 9.5 Operation .......................................................................................................................... 331 9.5.1 Endian/Access Size and Data Alignment.......................................................... 331 9.5.2 Normal Space Interface..................................................................................... 337 ...
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Section 11 Clock Pulse Generator (CPG)..........................................................455 11.1 Features............................................................................................................................. 455 11.2 Input/Output Pins.............................................................................................................. 459 11.3 Clock Operating Modes .................................................................................................... 460 11.4 Register Descriptions ........................................................................................................ 463 11.4.1 Frequency Control Register (FRQCR).............................................................. 463 11.4.2 USBH/USBF Clock Control Register (UCLKCR) ........................................... 466 11.5 Changing ...
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Transition to Software Standby Mode .............................................................. 491 13.5.2 Canceling Software Standby Mode................................................................... 491 13.6 Module Standby Function................................................................................................. 493 13.6.1 Transition to Module Standby Function ........................................................... 493 13.6.2 Canceling Module Standby Function................................................................ 493 13.7 STATUS Pin Change Timing ........................................................................................... 494 ...
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Timer Counters (TCNT) ................................................................................... 528 15.3.7 Timer General Registers (TGR)........................................................................ 528 15.3.8 Timer Start Register (TSTR)............................................................................. 529 15.4 Operation .......................................................................................................................... 530 15.4.1 Overview........................................................................................................... 530 15.4.2 Basic Functions................................................................................................. 531 15.4.3 Buffer Operation ............................................................................................... 536 15.4.4 PWM Modes ..................................................................................................... 538 15.4.5 ...
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Day of Week Alarm Register (RWKAR) ......................................................... 574 17.3.13 Date Alarm Register (RDAYAR) ..................................................................... 575 17.3.14 Month Alarm Register (RMONAR) ................................................................. 576 17.3.15 Year Alarm Register (RYRAR)........................................................................ 576 17.3.16 RTC Control Register 1 (RCR1)....................................................................... 577 17.3.17 RTC Control Register ...
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Usage Notes ...................................................................................................................... 639 Section 19 Infrared Data Association Module (IrDA).......................................641 19.1 Features............................................................................................................................. 641 19.2 Input/Output Pins.............................................................................................................. 642 19.3 Register Description.......................................................................................................... 642 19.3.1 IrDA Mode Register (SCIMR) ......................................................................... 642 19.4 Operation .......................................................................................................................... 644 19.4.1 Transmitting...................................................................................................... 644 19.4.2 Receiving .......................................................................................................... ...
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Section 21 Serial I/O with FIFO (SIOF) ...........................................................679 21.1 Features............................................................................................................................. 679 21.2 Input/Output Pins.............................................................................................................. 681 21.3 Register Descriptions........................................................................................................ 682 21.3.1 Mode Register (SIMDR)................................................................................... 683 21.3.2 Control Register (SICTR) ................................................................................. 686 21.3.3 Transmit Data Register (SITDR) ...................................................................... 689 21.3.4 Receive Data ...
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Ringing Pulse Counter (RCNT) ........................................................................ 746 22.3.7 AFE Control Data Register (ACDR) ................................................................ 746 22.3.8 AFE Status Data Register (ASDR) ................................................................... 746 22.3.9 Transmit Data FIFO Port (TDFP) ..................................................................... 747 22.3.10 Receive Data FIFO Port (RDFP) ...................................................................... 747 22.4 ...
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Hc Bulk Current ED Register (USBHBCED) .................................................. 781 24.3.13 Hc Done Head ED Register (USBHDHED) ..................................................... 781 24.3. Interval Register (USBHFI) .................................................................. 781 24.3.15 Hc Frame Remaining Register (USBHFR)....................................................... 783 24.3. Number b Register (USBHFN)............................................................. ...
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EP0i Data Register (EPDR0i) ........................................................................... 821 25.3.17 EP0o Data Register (EPDR0o) ......................................................................... 821 25.3.18 EP0s Data Register (EPDR0s) .......................................................................... 821 25.3.19 EP1 Data Register (EPDR1) ............................................................................. 822 25.3.20 EP2 Data Register (EPDR2) ............................................................................. 822 25.3.21 EP3 Data Register (EPDR3) ...
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Usage Notes ...................................................................................................................... 859 25.9.1 Setup Data Reception........................................................................................ 859 25.9.2 FIFO Clear ........................................................................................................ 859 25.9.3 Overreading/Overwriting of Data Register ....................................................... 859 25.9.4 Assigning EP0 Interrupt Sources ...................................................................... 860 25.9.5 FIFO Clear when DMA Transfer is Set ............................................................ 860 25.9.6 ...
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Data Format ...................................................................................................... 907 26.4.5 Setting the Display Resolution.......................................................................... 910 26.4.6 Power Management Registers........................................................................... 910 26.4.7 Operation for Hardware Rotation ..................................................................... 915 26.5 Clock and LCD Data Signal Examples............................................................................. 918 26.6 Usage Notes ...................................................................................................................... 928 26.6.1 Procedure for Halting ...
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Section 29 PC Card Controller (PCC)...............................................................957 29.1 Features............................................................................................................................. 957 29.1.1 PCMCIA Support ............................................................................................. 959 29.2 Input/Output Pins.............................................................................................................. 962 29.3 Register Descriptions........................................................................................................ 963 29.3.1 Area 6 Interface Status Register (PCC0ISR) .................................................... 963 29.3.2 Area 6 General Control Register (PCC0GCR) ................................................. 966 ...
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Section 31 MultiMediaCard Interface (MMCIF) ............................................1027 31.1 Features........................................................................................................................... 1027 31.2 Input/Output Pins............................................................................................................ 1029 31.3 Register Descriptions ...................................................................................................... 1030 31.3.1 Mode Register (MODER)............................................................................... 1031 31.3.2 Command Type Register (CMDTYR)............................................................ 1031 31.3.3 Response Type Register (RSPTYR) ............................................................... 1033 31.3.4 Transfer Byte Number ...
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Break Address Register B (BARB) ................................................................ 1116 33.2.5 Break Address Mask Register B (BAMRB) ................................................... 1117 33.2.6 Break Data Register B (BDRB) ...................................................................... 1117 33.2.7 Break Data Mask Register B (BDMRB)......................................................... 1118 33.2.8 Break Bus Cycle Register B (BBRB) ...
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Port U Control Register (PUCR) .................................................................... 1169 34.1.18 Port V Control Register (PVCR) .................................................................... 1170 34.1.19 Pin Select Register A (PSELA) ...................................................................... 1171 34.1.20 Pin Select Register B (PSELB) ....................................................................... 1173 34.1.21 Pin Select Register C (PSELC) ....................................................................... 1174 ...
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Register Description ....................................................................................... 1201 35.11.2 Port L Data Register (PLDR).......................................................................... 1202 35.12 Port M ............................................................................................................................. 1203 35.12.1 Register Description ....................................................................................... 1203 35.12.2 Port M Data Register (PMDR) ....................................................................... 1204 35.13 Port P .............................................................................................................................. 1205 35.13.1 Register Description ....................................................................................... 1205 ...
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Supported Instructions .................................................................................... 1234 36.5.2 Points for Attention......................................................................................... 1235 36.6 Usage Notes .................................................................................................................... 1236 36.7 Advanced User Debugger (AUD)................................................................................... 1236 Section 37 List of Registers .............................................................................1237 37.1 Register Addresses.......................................................................................................... 1238 37.2 Register Bits.................................................................................................................... 1255 37.3 Register States in Each ...
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Appendix ...........................................................................................................1377 A. Pin States ........................................................................................................................ 1377 B. Product Lineup................................................................................................................ 1390 C. Package Dimensions ....................................................................................................... 1392 Main Revisions for This Edition .......................................................................1395 Index .................................................................................................................1407 Page xxxii of lx R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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Section 1 Overview Figure 1.1 Block Diagram........................................................................................................ 10 Figure 1.2 Pin Assignments (PLBG0256GA-A (BP-256H/HV)) ............................................ 11 Figure 1.3 Pin Assignments (PLBG0256KA-A (BP-256C/CV))............................................. 12 Section 2 CPU Figure 2.1 Processing State Transitions ................................................................................... 38 Figure 2.2 Virtual Address to External Memory ...
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Figure 3.22 Local Data Move Instruction Flow ....................................................................... 147 Section 4 Memory Management Unit (MMU) Figure 4.1 MMU Functions.................................................................................................... 166 Figure 4.2 Virtual Address Space (MMUCR. ........................................................... 168 Figure 4.3 Virtual Address Space (MMUCR. ........................................................... 169 ...
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Figure 9.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) .................................. 340 Figure 9.6 Example of 32-Bit Data-Width SRAM Connection ............................................. 341 Figure ...
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Figure 9.39 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) .............................................................................................. 395 Figure 9.40 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10).................................. 396 Figure ...
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Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode (DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So DREQ Sampling is Accepted One Extra Time)........................................ 450 Figure 10.20 Timing ...
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Section 14 Timer Unit (TMU) Figure 14.1 Block Diagram of TMU........................................................................................ 502 Figure 14.2 Setting Count Operation ....................................................................................... 507 Figure 14.3 Auto-Reload Count Operation .............................................................................. 508 Figure 14.4 Count Timing when Internal Clock is Operating.................................................. 509 Figure 14.5 Count Timing ...
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Figure 17.4 Using Alarm Function .......................................................................................... 584 Figure 17.5 Using Periodic Interrupt Function ........................................................................ 585 Figure 17.6 Example of Crystal Oscillator Circuit Connection ............................................... 586 Section 18 Serial Communication Interface with FIFO (SCIF) Figure 18.1 Block Diagram of SCIF ........................................................................................ ...
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Section Bus Interface (IIC) Figure 20.1 Block Diagram of I Figure 20.2 External Circuit Connections of I/O Pins ............................................................. 649 2 Figure 20 Bus Formats .................................................................................................... 662 2 Figure 20 Bus Timing ...
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Figure 21.20 Transmit and Receive Timing (16-Bit Stereo Data) ............................................. 733 Figure 21.21 Frame Length (32-Bit) .......................................................................................... 734 Section 22 Analog Front End Interface (AFEIF) Figure 22.1 Block Diagram of AFE Interface .......................................................................... 735 Figure 22.2 FIFO Interrupt Timing .......................................................................................... ...
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Figure 25.16 EP5 Isochronous-In Transfer Operation (SOF is Normal).................................... 852 Figure 25.17 EP5 Isochronous-In Transfer Operation (SOF in Broken).................................... 853 Figure 25.18 Forcible Stall by Application................................................................................ 857 Figure 25.19 Automatic Stall by USB Function Controller ....................................................... 858 Figure 25.20 Set ...
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Figure 27.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)..................................................... 941 Figure 27.5 A/D Conversion Timing ....................................................................................... 942 Figure 27.6 External Trigger Input Timing.............................................................................. 943 Figure 27.7 Definitions of A/D Conversion Accuracy............................................................. 945 Figure 27.8 Analog ...
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Section 31 MultiMediaCard Interface (MMCIF) Figure 31.1 Block Diagram of MMCIF ................................................................................. 1028 Figure 31.2 Example of Command Sequence for Commands that do not Require Command Response............................................................ 1060 Figure 31.3 Operational Flow for Commands that do not Require Command Response ...
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Figure 31.20 Operational Flowchart for Commands with Write Data (Open-ended Multiblock Transfer) (1) ............................................................... 1083 Figure 31.20 Operational Flowchart for Commands with Write Data (Open-ended Multiblock Transfer) (2) ............................................................... 1084 Figure 31.21 Operational Flowchart for Commands with Write Data (Pre-defined ...
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Section 35 I/O Ports Figure 35.1 Port A.................................................................................................................. 1179 Figure 35.2 Port B.................................................................................................................. 1181 Figure 35.3 Port C.................................................................................................................. 1183 Figure 35.4 Port D.................................................................................................................. 1185 Figure 35.5 Port E .................................................................................................................. 1187 Figure 35.6 Port F .................................................................................................................. 1190 Figure 35.7 Port G.................................................................................................................. ...
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Figure 38.14 Basic Bus Cycle in Normal Space (External Wait 1 Input) ................................ 1326 Figure 38.15 Basic Bus Cycle in Normal Space (Software Wait 1, External Wait Valid (WM Bit = 0), No Idle Cycle) .............. 1327 Figure 38.16 CS ...
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Figure 38.32 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) ................. 1344 Figure 38.33 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Bank Active Mode: ...
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Figure 38.64 MMCIF Receive Timing (Rise Sampling).......................................................... 1371 Figure 38.65 TCK Input Timing .............................................................................................. 1372 Figure 38.66 TRST Input Timing (Reset Hold) ....................................................................... 1373 Figure 38.67 H-UDI Data Transfer Timing ............................................................................. 1373 Figure 38.68 ASEMD0 Input Timing ...................................................................................... 1373 Figure ...
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Page R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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Section 1 Overview Table 1.1 SH7720/SH7721 Features......................................................................................... 2 Table 1.2 Product Lineup (SH7720 Group).............................................................................. 8 Table 1.3 Product Lineup (SH7721 Group).............................................................................. 9 Table 1.4 List of Pin Assignments .......................................................................................... 13 Table 1.5 SH7720/SH7721 Pin Functions .............................................................................. 25 Section 2 CPU ...
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Table 3.16 DSR Register Bits................................................................................................. 116 Table 3.17 DSP Operation Instruction Formats...................................................................... 118 Table 3.18 Correspondence between DSP Instruction Operands and Registers ..................... 119 Table 3.19 DC Bit Update Definitions ................................................................................... 120 Table 3.20 Examples of NOPX and NOPY Instruction ...
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Section 6 X/Y Memory Table 6.1 X/Y Memory Virtual Addresses ........................................................................... 213 Table 6.2 MMU and Cache Settings..................................................................................... 216 Section 7 Exception Handling Table 7.1 Exception Event Vectors....................................................................................... 225 Table 7.2 Instruction Positions and Restriction Types.......................................................... 235 Table 7.3 SPC ...
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Table 9.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2..................................................................... 352 Table 9.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3) ........................................................................ 353 Table 9.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1..................................................................... 354 ...
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Section 14 Timer Unit (TMU) Table 14.1 TMU Interrupt Sources......................................................................................... 511 Section 15 16-Bit Timer Pulse Unit (TPU) Table 15.1 TPU Functions ...................................................................................................... 514 Table 15.2 TPU Pin Configurations........................................................................................ 516 Table 15.3 TPU Clock Sources............................................................................................... 520 Table 15.4 TPSC2 to ...
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Table 21.2 Operation in Each Transfer Mode......................................................................... 685 Table 21.3 SIOF Serial Clock Frequency ............................................................................... 710 Table 21.4 Serial Transfer Modes........................................................................................... 713 Table 21.5 Frame Length........................................................................................................ 714 Table 21.6 Audio Mode Specification for Transmit Data....................................................... 716 Table 21.7 Audio Mode ...
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Table 26.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates....... 913 Table 26.6 LCDC Operating Modes ....................................................................................... 914 Table 26.7 LCD Module Power-Supply States....................................................................... 914 Section 27 A/D Converter Table 27.1 Pin Configuration.................................................................................................. 931 Table 27.2 Analog Input Channels and ...
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Section 34 Pin Function Controller (PFC) Table 34.1 Multiplexed Pins................................................................................................. 1141 Section 35 I/O Ports Table 35.1 Port A Data Register (PADR) Read/Write Operations ....................................... 1180 Table 35.2 Port B Data Register (PBDR) Read/Write Operations ....................................... 1182 Table 35.3 Port ...
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Table 38.7 Clock Timing ...................................................................................................... 1315 Table 38.8 Control Signal Timing ........................................................................................ 1319 Table 38.9 Bus Timing ......................................................................................................... 1322 Table 38.10 Peripheral Module Signal Timing....................................................................... 1355 Table 38.11 16-Bit Timer Pulse Unit...................................................................................... 1356 Table 38.12 RTC Signal Timing............................................................................................. 1357 Table ...
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Page R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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SH7720 Group, SH7721 Group 1.1 Features This LSI is a single-chip RISC microprocessor that integrates a 32-bit RISC-type Super H architecture CPU with a digital signal processing (DSP) extension as its core, together with a large-capacity 32-kbyte cache memory, a ...
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Section 1 Overview Table 1.1 SH7720/SH7721 Features Item Features • CPU Renesas Original SuperH architecture • Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level • 32-bit internal data bus • General-register ⎯ Sixteen 32-bit general registers (eight ...
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SH7720 Group, SH7721 Group Item Features • 4-Gbyte address space, 256 address spaces (8-bit ASID) Memory • management unit Page unit sharing (MMU) • Supports multiple page sizes: 1 kbyte or 4 kbytes • 128-entry, 4-way set associative TLB • ...
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Section 1 Overview Item Features • Direct memory Number of channels: Six channels (two channels support external requests) access controller • Address space: 4 Gbytes on architecture (DMAC) • Data transfer length: Bytes, words (2 bytes), longwords (4 bytes), 16 ...
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SH7720 Group, SH7721 Group Item Features • 16-bit timer pulse Four-channel 16-bit timer unit (TPU) • PWM mode • Four types of counter input clocks • Phase counting mode (two channels) • Compare match Internal six-channel 32-bit counter (16-/32-bit switchable) ...
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Section 1 Overview Item Features • USB host Conforms to OHCI Rev. 1.0 controller (USBH) • USB Rev. 1.1 compatible • 127 endpoints • Support interrupt/bulk/control/isochronous mode • Bus master controller (can access area 3 and synchronous DRAM) • Two ...
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SH7720 Group, SH7721 Group Item Features • SIM card Single channel ready for ISO7816-3 data protocol ( interface (SIM) • Asynchronous half-duplex character transmission protocol • Data length of 8 bits • Generates and checks ...
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Section 1 Overview Item Features • User break Two break channels controller (UBC) • All of address, data value, access type, and data size can be set as break conditions. • Supports sequential break function • User debugging Supports E10A ...
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SH7720 Group, SH7721 Group Table 1.3 Product Lineup (SH7721 Group) Power Supply Voltage Operating Frequency Model I/O Internal SH7721 3.3 V 1.5 V 133.34 ±0.3V ±0.1V MHz [Legend] O: Provided; ⎯: Not provided R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 Product ...
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Section 1 Overview 1.2 Block Diagram User break Super H DSP core controller (UBC) CPU core X bus Y bus Cache access X/Y memory controller (CCN) Instruction/data for CPU/DSP (16 kbytes) Internal bus Bus state External bus Peripheral controller bus ...
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SH7720 Group, SH7721 Group Figure 1.2 Pin Assignments (PLBG0256GA-A (BP-256H/HV)) R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 Section 1 Overview Page 11 of 1414 ...
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Section 1 Overview Figure 1.3 Pin Assignments (PLBG0256KA-A (BP-256C/CV)) Page 12 of 1414 SH7720 Group, SH7721 Group R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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SH7720 Group, SH7721 Group Table 1.4 List of Pin Assignments Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name A1 A2 VssQ A2 D5 VccQ A3 D6 STATUS1/PTH3 A4 D7 LCD_DATA13/PINT13/ PTD5 A5 E6 VssQ A6 D8 ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name B6 C1 LCD_DATA15/PINT15/ PTD7 B7 B3 LCD_DATA11/PTD3 B8 E7 LCD_DATA7/PTC7 B9 D9 LCD_DATA3/PTC3 B10 E10 LCD_FLM/PTE0 B11 D11 LCD_M_DISP/PTE4 B12 E14 SIOF0_MCLK/PTS3 B13 E16 USB2_pwr_en/PTH1 ...
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SH7720 Group, SH7721 Group Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name C8 B9 LCD_DATA6/PTC6 C9 B10 LCD_DATA2/PTC2 C10 B11 LCD_DON/PTE1 C11 A12 SIOF0_SYNC/PTS4 C12 A13 SIOF0_TxD/PTS2 C13 A14 SIOF0_SCK/PTS0 ADTRG/PTF0 C14 E17 C15 D18 AN3/PTF4 ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name D9 A10 LCD_DATA0/PTC0 D10 E11 LCD_CL1/PTE3 D11 B12 Vss D12 B13 Vcc D13 B14 SIOF0_RxD/PTS1 USB2_ovr_current D14 B15 D15 D14 DA0/PTF5 D16 D15 AN1/PTF2 D17 ...
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SH7720 Group, SH7721 Group Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name E19 D21 USB1d_TXSE0/IRQ4/ AFE_TXOUT/ PCC_DRV/PTG5 E20 G21 VssQ F1 G2 D24/PTB0 F2 E2 D29/PTB5 F3 D4 D28/PTB4 F4 H4 D27/PTB3 F17 F17 MMC_VDDON/ SCIF1_CTS/ ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name H1 J1 VccQ1 H2 H1 D23/PTA7 H3 F5 D22/PTA6 H4 G5 Vss H17 J18 Vcc H18 H17 SIM_RST/SCIF1_RxD/ SD_WP/PTV1 H19 H21 SIM_D/SCIF1_TxD/ SD_CD/PTV2 H20 K20 ...
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SH7720 Group, SH7721 Group Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name K3 J5 D18/PTA2 K4 L4 D16/PTA0 K17 L20 SCIF0_TxD/IrTx/PTT2 SCIF0_CTS/TPU_TO1/ K18 K18 PTT4 K19 K21 MMC_CLK/SIOF1_SCK/ SD_CLK/TPU_TI2A/ PTU0 K20 M17 VssQ L1 K5 CKIO ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name M19 M18 IRQ0/IRL0/PTP0 M20 P17 IRQ2/IRL2/PTP2 RAS/PTH6 N1 M2 CS3 N2 P1 CS2 Vcc N17 N21 Vss N18 P20 AUDATA2/PTJ3 N19 ...
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SH7720 Group, SH7721 Group Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name A12 T17 U20 TMS/PTL6 T18 T18 TCK/PTL3 T19 U21 PINT7/PCC_RESET/ PTK3 ASEBRKAK/PTJ5 T20 V18 U1 R4 ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name U19 V21 PINT6/PCC_RDY/PTK2 U20 W20 TDO/PTL5 V1 U1 VccQ1 AA6 D12 V5 Y4 D14 V6 AA7 D9 V7 ...
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SH7720 Group, SH7721 Group Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name AA2 A2 W3 AA1 A1 W4 AA4 A0/PTR0 W5 AA5 D15 W6 V7 D10 ...
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Section 1 Overview Pin No. Pin No. (PLBG (PLBG 0256 0256 GA-A) KA-A) Pin Name Y7 U6 VssQ1 Y8 U7 VccQ1 CS6A/CE2B Y9 U8 Y10 AA11 VssQ1 Y11 U10 VccQ1 CS0 Y12 Y11 RD Y13 Y12 Y14 Y13 VssQ1 Y15 ...
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SH7720 Group, SH7721 Group 1.3.2 Pin Functions Table 1.5 lists the pin functions. Table 1.5 SH7720/SH7721 Pin Functions Classification Symbol Power supply Vcc Vss VccQ VssQ VccQ1 VssQ1 Clock Vcc_PLL1 Vss_PLL1 Vcc_PLL2 Vss_PLL2 EXTAL R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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Section 1 Overview Classification Symbol Clock XTAL CKIO Operating mode MD5 to MD0 control RESETP System control RESETM STATUS1, STATUS0 BREQ BACK CA Interrupts NMI IRQ5 to IRQ0 IRL3 to IRL0 Page 26 of 1414 I/O Name Function O Crystal ...
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SH7720 Group, SH7721 Group Classification Symbol Interrupts PINT15 to PINT0 REFOUT IRQOUT Address bus A25 to A0 Data bus D31 to D0 CS4 to CS2, Bus control CS0 CS6A, CS6B, CS5A, CS5B, CE2A, CE2B, CE1A, CE1B RD RD/WR BS BACK ...
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Section 1 Overview Classification Symbol CAS Bus control DQMUU DQMUL DQMLU DQMLL RAS WAIT IOIS16 ICIORD ICIOWR DREQ0, Direct memory DREQ1 access controller (DMAC) DACK0, DACK1 TEND0, TEND1 16-bit timer pulse TPU_TO3 to unit (TPU) TPU_TO0 TPU_TI3A to TPU_TI2A TPU_TI2B ...
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SH7720 Group, SH7721 Group Classification Symbol Analog front end AFE_TXOUT interface (AFEIF) AFE_RDET AFE_HC1 AFE_RXIN Serial SCIF0_TxD, communication SCIF1_TxD interface with SCIF0_RxD, FIFO SCIF1_RxD (SCIF) SCIF0_SCK, SCIF1_SCK SCIF0_RTS, SCIF1_RTS SCIF0_CTS, SCIF1_CTS IrDA IrTX IrRX Serial I/O with SIOF0_SYNC, FIFO (SIOF) ...
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Section 1 Overview Classification Symbol Realtime clock Vcc_RTC (RTC) Vss_RTC EXTAL_RTC XTAL_RTC LCD controller LCD_DATA15 (LCDC) to LCD_DATA0 LCD_CL1 LCD_CL2 LCD_CLK LCD_FLM LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP PC card PCC_BVD1 controller (PCC) PCC_BVD2 PCC_RDY PCC_REG PCC_RESET PCC_CD1 Page 30 of 1414 ...
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SH7720 Group, SH7721 Group Classification Symbol PCC_CD2 PC card controller (PCC) PCC_WAIT PCC_DRV PCC_VS1 PCC_VS2 PCC_IOIS16 MMC_ODMOD O MultiMedia Card interface (MMCIF) MMC_VDDON MMC_CLK MMC_DAT MMC_CMD SD host interface SD_CLK (SDHI) SD_CMD SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 R01UH0083EJ0400 Rev. 4.00 Sep ...
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Section 1 Overview Classification Symbol SD host interface SD_CD (SDHI) SD_WP SIM card module SIM_RST (SIM) SIM_CLK SIM_D A/D converter AN3 to AN0 (ADC) AVcc AVss ADTRG D/A converter DA0 (DAC) DA1 USB AVcc_USB AVss_USB EXTAL_USB XTAL_USB USB1_ovr_ current/ USBF_VBUS ...
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SH7720 Group, SH7721 Group Classification Symbol USB USB1_pwr_en/ USBF_UPLUP SUB2_pwer_en O USB1_P USB1_M USB2_P USB2_M USB1d_DMNS USB1d_ SUSPEND USB1d_RCV USB1d_TXENL O USB1d_SPEED O USB1d_TXSE0 O USB1d_ TXDPLS USB1d_DPLS I/O port PTA7 to PTA0 PTB7 to PTB0 PTC7 to PTC0 PTD7 ...
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Section 1 Overview Classification Symbol I/O port PTG6 to PTG0 PTH6 to PTH0 PTJ6 to PTJ0 PTK3 to PTK0 PTL7 to PTL3 PTM7 to PTM0 I/O PTP4 to PTP0 PTR7 to PTR0 PTS4 to PTS0 PTT4 to PTT0 PTU4 to ...
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SH7720 Group, SH7721 Group Classification Symbol Advanced user AUDATA3 to debugger AUDATA0 (AUD) AUDCK AUDSYNC ASEBRKAK E10A interface ASEMD0 Notes: 1. All Vcc/Vss/VccQ/VssQ/VccQ1/VssQ1/AVcc/AVss/AVcc_USB/AVss_USB/VccQ_RTC/ Vcc_RTC/Vss_RTC/Vcc_PLL1/Vss_PLL1/Vcc_PLL2/Vss_PLL2 should be connected to the system power supply (so that power is supplied at all times.) ...
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Section 1 Overview Page 36 of 1414 SH7720 Group, SH7721 Group R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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SH7720 Group, SH7721 Group 2.1 Processing States and Processing Modes 2.1.1 Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the ...
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Section 2 CPU 2.1.2 Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) in the status register (SR). If the MD bit is cleared ...
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SH7720 Group, SH7721 Group 2.2 Memory Map 2.2.1 Virtual Address Space The LSI supports 32-bit virtual addresses and accesses system resources using the 4-Gbytes of virtual address space. User programs and data are accessed from the virtual address space. The ...
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Section 2 CPU (5) P4 Area The P4 area is defined as a control area which is non-cacheable and non-address translatable. This area can be accessed only in privileged mode. A part of the LSI’s on-chip I/O is assigned to ...
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SH7720 Group, SH7721 Group Notes access an on-chip I/O mapped into area 1 in the external memory space, access the address from the P2 area which is not cached in the virtual address space the address ...
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Section 2 CPU 2.3 Register Descriptions This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. (1) General Registers This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 ...
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SH7720 Group, SH7721 Group Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each process mode. Table 2.2 Register Initial Values Register Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 ...
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Section 2 CPU 31 *1,*2 R0_BANK0 *2 R1_BANK0 *2 R2_BANK0 *2 R3_BANK0 *2 R4_BANK0 *2 R5_BANK0 *2 R6_BANK0 *2 R7_BANK0 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC (a) User mode register configuration Notes: ...
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SH7720 Group, SH7721 Group 2.3.1 General Registers There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15 are banked. The process mode and the register bank (RB) bit in the status ...
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Section 2 CPU 31 *1,* R10 R11 R12 R13 R14 R15 2.3.2 System Registers The system registers: multiply and accumulate registers (MACH/MACL) and ...
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SH7720 Group, SH7721 Group 2.3.3 Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. There is no instruction to read the PC directly. Before an exception handling state is entered, the ...
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Section 2 CPU 2.3.4 Control Registers The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC instruction in privileged mode. The GBR register can be accessed in the user mode. The control registers ...
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SH7720 Group, SH7721 Group Initial Bit Bit Name Value ⎯ All 0 ⎯ ⎯ All 1 ⎯ All 0 ⎯ ...
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Section 2 CPU Initial Bit Bit Name Value ⎯ Note: The and T bits can be set/cleared by the user mode specific instructions. Other bits can be read or written in privileged mode. (2) Save ...
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SH7720 Group, SH7721 Group Figure 2.6 shows the control register configuration. Save status register (SSR) 31 Save program counter (SPC) 31 Global base register (GBR) 31 Vector base register (VBR) 31 Status register (SR ...
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Section 2 CPU 2.4.2 Memory Data Formats Memory data formats are classified into byte, word, and longword. Memory can be accessed in byte, word, and longword. When the memory operand is only a byte (8 bits word (16 ...
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SH7720 Group, SH7721 Group The little endian mode can also be specified as data format. Either big-endian or little-endian mode can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor operates in ...
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Section 2 CPU 2.5 Features of CPU Core Instructions 2.5.1 Instruction Execution Method (1) Instruction Length All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the sequential pipeline, almost all instructions can ...
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SH7720 Group, SH7721 Group (4) T Bit The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Processing speed ...
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Section 2 CPU 2.5.2 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions Addressing Instruction Mode Format ...
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SH7720 Group, SH7721 Group Addressing Instruction Mode Format Register @(disp:4, indirect with Rn) displacement Indexed @(R0, Rn) register indirect GBR indirect with @(disp:8, displacement GBR) Indexed GBR @(R0, GBR) Effective address is sum of register GBR and R0 indirect R01UH0083EJ0400 ...
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Section 2 CPU Addressing Instruction Mode Format PC-relative with @(disp:8, displacement PC) PC-relative disp:8 disp:12 Rn Page 58 of 1414 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is zero-extended multiplied ...
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SH7720 Group, SH7721 Group Addressing Instruction Mode Format Immediate #imm:8 #imm:8 #imm:8 Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x1, x2, or x4) according ...
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Section 2 CPU 2.5.3 Instruction Formats Table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following ...
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SH7720 Group, SH7721 Group Instruction Format nm type 15 0 xxxx nnnn xxxx mmmm md type 15 0 xxxx xxxx dddd mmmm nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn dddd mmmm R01UH0083EJ0400 Rev. ...
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Section 2 CPU Instruction Format d type 15 0 xxxx xxxx dddd dddd d12 type 15 0 xxxx dddd dddd dddd nd8 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx ...
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SH7720 Group, SH7721 Group 2.6 Instruction Set 2.6.1 Instruction Set Based on Functions Table 2.5 shows the instructions classified by function. Table 2.5 CPU Instruction Types Kinds of Type Instruction Data transfer 5 instructions Arithmetic 21 operation instructions R01UH0083EJ0400 Rev. ...
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Section 2 CPU Kinds of Type Instruction Arithmetic 21 operation instructions Logic 6 operation instructions Shift 12 instructions Page 64 of 1414 Op Code Function Signed multiplication (16 × 16 bits) MULS Unsigned multiplication (16 × 16 bits) MULU NEG ...
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SH7720 Group, SH7721 Group Kinds of Type Instruction Branch 9 instructions System 15 control instructions Total: 68 The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, ...
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Section 2 CPU Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST mmmm: Source register OP: Operation code nnnn: Destination register Sz: Size 0000: R0 SRC: Source 0001: ...
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SH7720 Group, SH7721 Group Table 2.6 Data Transfer Instructions Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn 0110nnnnmmmm0011 MOV.B Rm,@Rn 0010nnnnmmmm0000 MOV.W Rm,@Rn 0010nnnnmmmm0001 MOV.L Rm,@Rn 0010nnnnmmmm0010 MOV.B @Rm,Rn 0110nnnnmmmm0000 MOV.W @Rm,Rn 0110nnnnmmmm0001 ...
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Section 2 CPU Instruction Instruction Code Operation MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT Rn 0000nnnn00101001 ...
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SH7720 Group, SH7721 Group Table 2.7 Arithmetic Operation Instructions Instruction Instruction Code Operation ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 ...
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Section 2 CPU Instruction Instruction Code Operation EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+, 0000nnnnmmmm1111 @Rn+ MAC.W @Rm+, 0100nnnnmmmm1111 @Rn+ MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC ...
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SH7720 Group, SH7721 Group Table 2.8 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0, 11001101iiiiiiii GBR) NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0, 11001111iiiiiiii GBR) TAS.B @Rn 0100nnnn00011011 TST Rm,Rn ...
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Section 2 CPU Table 2.9 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm, Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm, Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 SHLR ...
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SH7720 Group, SH7721 Group Table 2.10 Branch Instructions Instruction Instruction Code BF disp 10001011dddddddd BF/S disp 10001111dddddddd BT disp 10001001dddddddd BT/S disp 10001101dddddddd BRA disp 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR disp 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm ...
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Section 2 CPU Table 2.11 System Control Instructions Instruction Instruction Code Operation CLRMAC 0000000000101000 CLRS 0000000001001000 CLRT 0000000000001000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC Rm,SSR 0100mmmm00111110 LDC Rm,SPC 0100mmmm01001110 LDC Rm,R0_BANK 0100mmmm10001110 LDC Rm,R1_BANK 0100mmmm10011110 LDC ...
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SH7720 Group, SH7721 Group Instruction Instruction Code Operation LDC.L @Rm+, 0100mmmm11010111 R5_BANK LDC.L @Rm+, 0100mmmm11100111 R6_BANK LDC.L @Rm+, 0100mmmm11110111 R7_BANK LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 LDS.L @Rm+,MACL 0100mmmm00010110 LDS.L @Rm+,PR 0100mmmm00100110 LDTLB 0000000000111000 ...
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Section 2 CPU Instruction Instruction Code STC R7_BANK,Rn 0000nnnn11110010 STC.L SR,@–Rn 0100nnnn00000011 STC.L GBR,@–Rn 0100nnnn00010011 STC.L VBR,@–Rn 0100nnnn00100011 STC.L SSR,@–Rn 0100nnnn00110011 STC.L SPC,@–Rn 0100nnnn01000011 STC.L R0_BANK,@–Rn 0100nnnn10000011 STC.L R1_BANK,@–Rn 0100nnnn10010011 STC.L R2_BANK,@–Rn 0100nnnn10100011 STC.L R3_BANK,@–Rn 0100nnnn10110011 STC.L R4_BANK,@–Rn 0100nnnn11000011 STC.L ...
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SH7720 Group, SH7721 Group 1. Number of states before the chip enters the sleep state. 2. For details, refer to section 7, Exception Handling. 2.6.2 Operation Code Map Table 2.12 shows the operation code map. Table 2.12 Operation Code Map ...
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Section 2 CPU Instruction Code Fx: 0000 MSB LSB MD: 00 0010 Rn Rm 11MD CMP/STR Rm, Rn 0011 Rn Rm 00MD CMP/EQ Rm, Rn 0011 Rn Rm 01MD DIV1 0011 Rn Rm 10MD SUB 0011 Rn Rm 11MD ADD ...
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SH7720 Group, SH7721 Group Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rm 00MD 1110 LDC 0100 Rm 01MD 1110 LDC 0100 Rm 10MD 1110 LDC 0100 Rm 11MD 1110 LDC 0100 Rn Rm 1111 MAC.W 0101 Rn Rm ...
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Section 2 CPU Page 80 of 1414 SH7720 Group, SH7721 Group R01UH0083EJ0400 Rev. 4.00 Sep 21, 2010 ...
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SH7720 Group, SH7721 Group Section 3 DSP Operating Unit 3.1 DSP Extended Functions This LSI incorporates a DSP unit and X/Y memory directly connected to the DSP unit. This LSI supports the DSP extended function instruction sets needed to control ...
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Section 3 DSP Operating Unit (4) DSP Unit Operation Instructions DSP unit operation instructions are called DSP data operation instructions. These instructions are provided to execute digital signal processing operations at high speed using the DSP. Instruction codes for these ...
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SH7720 Group, SH7721 Group 3.2 DSP Mode Resources 3.2.1 Processing Modes The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) in the status register (SR), as shown below. Table 3.1 CPU Processing Modes ...
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Section 3 DSP Operating Unit 3.2.3 CPU Register Sets In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three control registers: a repeat start register (SR), repeat end register (RE), and ...
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SH7720 Group, SH7721 Group (1) Extension of Status Register (SR) In DSP mode, the following control bits are added to the status register (SR). These added bits are called DSP extension bits. These DSP extension bits are valid only in ...
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Section 3 DSP Operating Unit (2) Repeat Start Register (RS) The repeat start register (RS) holds the start address of a loop repeat module that is controlled by the repeat function. This register can be accessed in DSP mode. At ...
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SH7720 Group, SH7721 Group Table 3.3 Operation of SR Bits in Each Processing Mode Privileged Mode User Mode & & DSP = 0 DSP = 0 Field ...
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Section 3 DSP Operating Unit Before entering the exception handling state, all bits including the DSP extension bits of the SR registers are saved in the SSR. Before returning from the exception handling, all bits including the DSP extension bits ...
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SH7720 Group, SH7721 Group 3.3 CPU Extended Instructions 3.3.1 DSP Repeat Control In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this function, loop programs can be executed without overhead caused by the compare ...
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Section 3 DSP Operating Unit more instructions, the same instruction is regarded as the RptStart instruction and RptDtct instruction. To control the repeat loop, the DSP extended control registers, such as the RE register and RS register and the RC[11:0] ...
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SH7720 Group, SH7721 Group • Example 2: Repeat loop consisting of three instructions LDRS RptDtct +4 LDRE RptDtct +4 SETRC #4 RptDtct: instr0 RptStart: instr1 Instr2 RptEnd: instr3 • Example 3: Repeat loop consisting of two instructions LDRS RptDtct +6; ...
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Section 3 DSP Operating Unit • Example 4: Repeat loop consisting of one instruction LDRS RptDtct +8; Sets (repeat detection instruction LDRE RptDtct +4 SETRC #4 RptDtct: instr0 RptStart: RptEnd: instr1 In repeat loops consisting of three instructions, two instructions ...
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SH7720 Group, SH7721 Group Table 3.4 shows the addresses to be specified in the repeat start register (RS) and repeat end register (RE). Table 3.4 RS and RE Setting Rule 1 RS RptStart0 + 8 RE RptStart0 + 4 Note: ...
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Section 3 DSP Operating Unit The RS and RE registers must be specified appropriately according to the rules shown in table 3.4. The SH assembler supports control macros (REPEAT) as shown in table 3.6 to solve problems. Table 3.6 Repeat ...
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SH7720 Group, SH7721 Group • Example 6: Repeat loop consisting of three instructions (extended to the instruction stream shown in example 2, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 instr2 RptEnd: instr3 • Example 7: Repeat loop consisting of ...
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Section 3 DSP Operating Unit Table 3.7 DSP Mode Extended System Control Instructions Instruction Operation STC RS, Rn RS→Rn STC RE, Rn RE→Rn STC.L RS, @-Rn Rn-4→Rn, RS→(Rn) STC.L RE, @-Rn Rn-4→Rn, RE→(Rn) LDC.L @Rn+, RS (Rn)→RS, Rn+4→Rn LDC.L @Rn+, ...
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SH7720 Group, SH7721 Group (c) Instructions prohibited during repeat loop (In a repeat loop consisting of four or more instructions) The following instructions must not be placed between the repeat start instruction and repeat detection instruction in a repeat loop ...
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Section 3 DSP Operating Unit Notes TRAPA instruction is used as a repeat detection instruction, an instruction following the repeat detection instruction is regarded as a return address. In this case, a control cannot be returned to ...
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SH7720 Group, SH7721 Group • PC relative addressing instructions MOV.A @(disp, PC), Rn MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn (Including the case when the MOV #imm,Rn is extended to MOV.W @(disp, PC MOV.L @(disp, PC), Rn) ...
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Section 3 DSP Operating Unit 3.4 DSP Data Transfer Instructions In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added instructions are classified into the following three groups. 1. Double data transfer instructions The ...
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SH7720 Group, SH7721 Group XAB [15:0] X memory Y memory Legend XAB : X bus (address) XDB : X bus (data) YAB : Y bus (address) YDB : Y bus (data) LAB : L bus (address) LDB : L bus ...
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Section 3 DSP Operating Unit Double data transfer instructions can be described in parallel to the DSP operation instructions. Even if a conditional operation instruction is specified in parallel to a double data transfer instruction, the specified condition does not ...
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SH7720 Group, SH7721 Group (3) System control instructions The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system registers. Accordingly, data transfer operations between these DSP system registers and ...
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Section 3 DSP Operating Unit 3.4.1 General Registers The DSP instructions 10 general registers in the 16 general registers are used as address pointers or index registers for double data transfers and single data transfers. In the following descriptions, another ...
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SH7720 Group, SH7721 Group In assembler are used as symbols. In the DSP data transfer instructions, the following register names (alias) can also be used. In assembler, described as shown below. Ix: .REG (R8) Ix indicates the ...
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Section 3 DSP Operating Unit 3.4.2 DSP Data Addressing Table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. Table 3.10 Overview of Data Transfer Instructions Double Data Transfer Instructions MOVX.W MOVY.W Address register ...
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SH7720 Group, SH7721 Group (1) Addressing Mode for Double Data Transfer Instructions The double data transfer instructions supports the following three addressing modes. • Non-update address register addressing The Ax and Ay registers are address pointers. They are not updated. ...
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Section 3 DSP Operating Unit In single data transfer instructions, all bits in 32-bit address are valid. 3.4.3 Modulo Addressing In double data transfer instructions, a module addressing can be used. If the address pointer value reaches the preset modulo ...
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SH7720 Group, SH7721 Group An example of the use of modulo addressing is shown below. MOV.L #H’70047000, R10 LDC R10,MOD STC SR, R10 MOV.L #H’FFFFF3FF, R11; MOV.L #H’00000400, R12; AND R11, R10 OR R12, R10 LDC R10, SR MOV.L #H’A5007000, ...
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Section 3 DSP Operating Unit 3.4.4 Memory Data Formats Memory data formats that can be used in the DSP instructions are classified into byte and longword. An address error will occur if word data starting from an address other than ...
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SH7720 Group, SH7721 Group 3.4.5 Instruction Formats of Double and Single Transfer Instructions The format of double data transfer instructions is shown in tables 3.12 and that of single data transfer instructions in table 3.13. Table 3.12 Double Data Transfer ...
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Section 3 DSP Operating Unit Table 3.13 Single Data Transfer Instruction Formats Type Mnemonic Single data MOVS.W @-As,Ds transfer MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L ...
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SH7720 Group, SH7721 Group 3.5 DSP Data Operation Instructions 3.5.1 DSP Registers This LSI has eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register (DSR) as DSP registers (figure 3.3). Four kinds of ...
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Section 3 DSP Operating Unit example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details of register selectability. Table 3.14 Destination Register in DSP Instructions Registers Instructions A0, A1 DSP Fixed-point, PSHA, operation ...
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SH7720 Group, SH7721 Group Table 3.15 Source Register in DSP Operations Registers Instructions A0, A1 DSP Fixed-point, PDMSB, operation PSHA Integer Logical, PSHL, PMULS Data MOVX/Y.W, MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 DSP Fixed-point, PDMSB, ...
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Section 3 DSP Operating Unit Table 3.16 DSR Register Bits Initial Value Bits Bit Name ⎯ All All 0 Page ...
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SH7720 Group, SH7721 Group Initial Bits Bit Name Value The DSR is assigned to the system registers. For the DSR, the following load and store instructions are supported. STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; If ...
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Section 3 DSP Operating Unit 3.5.2 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The ...
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SH7720 Group, SH7721 Group Table 3.18 Correspondence between DSP Instruction Operands and Registers Register Yes A1 Yes M0 Yes M1 Yes X0 Yes X1 Yes Y0 Yes Y1 Yes When writing parallel instructions, the field-B instruction is ...
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Section 3 DSP Operating Unit Table 3.19 DC Bit Update Definitions CS [2:0] Condition Mode Carry or borrow mode Negative value mode Zero value mode Overflow mode 1 ...
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SH7720 Group, SH7721 Group • Conditional Operations and Data Transfer Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid ...
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Section 3 DSP Operating Unit Table 3.20 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 MOVX.W @R4+,X0 NOPY MOVS.W ...
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SH7720 Group, SH7721 Group 3.5.3 DSP-Type Data Formats This LSI has several different data formats that depend on the instruction. This section explains the data formats for DSP type instructions. Figure 3.8 shows three DSP-type data formats with different binary ...
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Section 3 DSP Operating Unit DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer With guard bits Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) DSP type ...
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SH7720 Group, SH7721 Group 3.5.4 ALU Fixed-Point Arithmetic Operations Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers ...
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Section 3 DSP Operating Unit Table 3.21 Variation of ALU Fixed-Point Operations Mnemonic Function PADD Addition PSUB Subtraction PADDC Addition with carry PSUBC Subtraction with borrow PCMP Comparison PCOPY Data copy PABS Absolute PNEG Negation PCLR Clear Table 3.22 Correspondence ...
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SH7720 Group, SH7721 Group Operation Sequence Example MOVX.W @ PADD X0, Y0, A0 MOVX.W @ Slot 1 Stage IF MOVX ID EX MA/DSP Figure 3.10 Operation Sequence Example Every time an ALU arithmetic operation is executed, ...
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Section 3 DSP Operating Unit (1) Carry or Borrow Mode: CS[2:0] = B'000 The DC bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. Some examples are shown ...
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SH7720 Group, SH7721 Group (2) Negative Value Mode: CS[2:0] = B'001 The DC flag indicates the same value as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is ...
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Section 3 DSP Operating Unit (5) Signed Greater Than Mode: CS[2:0] = B'100 The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. ...
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SH7720 Group, SH7721 Group 3.5.5 ALU Integer Operations Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point ...
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Section 3 DSP Operating Unit In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in ALU integer arithmetic operations ...
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SH7720 Group, SH7721 Group 3.5.6 ALU Logical Operations Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of operation. The correspondence between each operand and registers is the same as the ALU fixed- ...
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Section 3 DSP Operating Unit Every time an ALU logical operation is executed, the DC and GT bits in the DSR register are basically updated in accordance with the operation result. In case of a conditional operation, ...
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SH7720 Group, SH7721 Group 3.5.7 Fixed-Point Multiply Operation Figure 3.16 shows the multiply operation flow. Table 3.25 shows the variation of this type of operation and table 3.26 shows the correspondence between each operand and registers. The multiply operation of ...
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Section 3 DSP Operating Unit Table 3.26 Correspondence between Operands and Registers Register Se ⎯ Yes ⎯ M0 ⎯ Yes X1 Yes Y0 Yes ⎯ Y1 Note: The multiply operations basically generate 32-bit operation results. So ...
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SH7720 Group, SH7721 Group 3.5.8 Shift Operations Shift operations can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations of arithmetic ...
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Section 3 DSP Operating Unit Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard- bit ...
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SH7720 Group, SH7721 Group The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state ...
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Section 3 DSP Operating Unit Every time a logical shift operation is executed, the DC and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are ...