HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet
HD6417750SF167V
Specifications of HD6417750SF167V
Available stocks
Related parts for HD6417750SF167V
HD6417750SF167V Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7750, SH7750S, 32 SH7750R Group Hardware Manual ...
Page 4
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
Page 5
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
Page 6
Rev.7.00 Oct. 10, 2008 Page iv of lxxxiv REJ09B0366-0700 ...
Page 7
The SH-4 (SH7750 Group: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Group is built in with a variety of peripheral functions such as ...
Page 8
User manuals for development tools Name of Document SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH™ RISC engine Simulator/Debugger User's Manual High-performance Embedded Workshop User's Manual Rev.7.00 Oct. 10, 2008 Page vi of lxxxiv REJ09B0366-0700 ...
Page 9
Main Revisions for This Edition Item Page ⎯ All 1.1 SH7750, SH7750S, 1 SH7750R Groups Features Table 1.1 LSI Features Table amended Revision (See Manual for Details) • Notification of change in company name amended (Before) ...
Page 10
Item Page 1.2 Block Diagram 9 Figure 1.1 Block Diagram of SH7750/ SH7750S/SH7750R Group Functions Rev.7.00 Oct. 10, 2008 Page viii of lxxxiv REJ09B0366-0700 Revision (See Manual for Details) Figure amended CPU UBC Lower 32-bit data Lower 32-bit data Cache ...
Page 11
Item Page 1.3 Pin Arrangement 12 Figure 1.4 Pin Arrangement (264-Pin CSP) Figure 1.5 Pin 13 Arrangement (292-Pin BGA) 1.4.1 Pin Functions 17, 20, (256-Pin BGA) 23 Table 1.2 Pin Functions Revision (See Manual for Details) Figure amended 1 2 ...
Page 12
Item Page 1.4.2 Pin Functions 26, 27, (208-Pin QFP) 31 Table 1.3 Pin Functions 1.4.3 Pin Functions 35, 38, (264-Pin CSP) 41 Table 1.4 Pin Functions 1.4.4 Pin Functions Newly added (292-Pin BGA) 2.2.1 Privileged Mode 55 ...
Page 13
Item Page 4.3.10 Notes on Using 125 to Cache Enhanced Mode 127 (SH7750R Only) 4.4.1 Configuration 130 • LRU (SH7750R only) 5.3.2 Exception 151 Handling Vector Addresses 5.5.3 Exception 158 Requests and BL Bit 5.6.1 Resets 159 (1) Power-On Reset ...
Page 14
Item Page 5.6.1 Resets 161 (3) H-UDI Reset (4) Instruction TLB 162 Multiple-Hit Exception (5) Operand TLB 163 Multiple-Hit Exception 5.6.2 General 174 Exceptions (11) General FPU Disable Exception 5.6.3 Interrupts 180 (3) Peripheral Module Interrupts Rev.7.00 Oct. 10, 2008 ...
Page 15
Item Page 5.7 Usage Notes 182 6.5 Floating-Point 194 Exceptions • Enable/disable exception handling 6.6.2 Pair Single- 196 Precision Data Transfer 6.7 Usage Notes 197 to 207 Revision (See Manual for Details) Description amended general exception or ...
Page 16
Item Page 7.3 Instruction Set 227 Table 7.12 Floating- Point Graphics Acceleration Instructions 7.4 Usage Notes 227 to 229 8.4 Usage Notes 258 9.1.1 Types of Power- 259 Down Modes 9.2.4 Standby Control 266 Register 2 (STBCR2) 9.5.2 Exit from ...
Page 17
Item Page 9.7.2 Exit from 274 Hardware Standby Mode 9.7.3 Usage Notes 275 9.8.1 In Reset 276 Figure 9.2 STATUS Output in Manual Reset 9.8.5 Hardware 285 Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.15 Timing When VDD-RTC Power is ...
Page 18
Item Page 10.1.1 Features 287 10.3 Clock Operating 294 Modes Table 10.4 FRQCR Settings and Internal Clock Frequencies 10.11 Usage Notes 309 11.1 Overview 311 11.2.16 RTC Control 326 Register 2 (RCR2) Bit 3— Oscillation Circuit Enable (RTCEN): 11.5.4 RTC ...
Page 19
Item Page 13.1.2 Block Diagram 359 Figure 13.1 Block Diagram of BSC 13.1.3 Pin 360 Configuration Table 13.1 BSC Pins 13.1.6 PCMCIA 371 Support Table 13.5 PCMCIA Support Interfaces 13.2.1 Bus Control 372 Register 1 (BCR1) 13.2.7 Wait Control 400 ...
Page 20
Item Page 13.2.8 Memory Control 402 Register (MCR) Bit 31—RAS Down (RASD): Bits 29 to 27—RAS 402 Precharge Time at End of Refresh (TRC2– TRC0) Bits 21 to 19—RAS 403 Precharge Period (TPC2–TPC0): Bits 15 to 13—Write 404 Precharge Delay ...
Page 21
Item Page 13.3.4 DRAM Interface 463 Refresh Timing: • Self-Refresh 13.3.5 Synchronous 465 DRAM Interface Revision (See Manual for Details) Description deleted After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately ...
Page 22
Item Page 13.3.5 Synchronous 466 DRAM Interface Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) Figure 13.27 Example 467 of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Figure 13.37 Burst 481 Write Timing (Different Row ...
Page 23
Item Page 13.3.5 Synchronous 491 DRAM Interface Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Connecting a 128- 494, 495 Description amended Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): Figure 13.46 496 Synchronous DRAM Auto-Refresh ...
Page 24
Item Page 13.3.7 PCMCIA 508 Interface Figure 13.54 Basic Timing for PCMCIA I/O Card Interface Figure 13.55 Wait 509 Timing for PCMCIA I/O Card Interface 13.3.8 MPX Interface 512 Figure 13.57 Example of 64-Bit Data Width MPX Connection Figure 13.66 ...
Page 25
Item Page 13.3.8 MPX Interface 523 Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Figure 13.69 MPX 524 Interface Timing 12 (Burst Write Cycle, ...
Page 26
Item Page 14.3.2 DMA Transfer 569 Requests 14.3.4 Types of DMA 582 Transfer Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.8 External 583 Request Transfer Sources and Destinations in Normal DMA Mode 14.3.5 Number ...
Page 27
Item Page 14.5.2 Pins in DDT 605 Mode Figure 14.24 System Configuration in On- Demand Data Transfer Mode TR: Transfer request • signal 608 14.8.3 Transfer 648 Channel Notification in DDT Mode Table 14.16 Function of BAVL 14.9 Usage Notes ...
Page 28
Item Page 15.3.3 Multiprocessor 702 to Communication 704 Function Multiprocessor Serial Data Reception: Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Figure 15.16 Example 706 of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 15.5 Usage ...
Page 29
Item Page 16.1.3 Pin 728 Configuration Table 16.1 SCIF Pins 16.2.9 FIFO Control 747 Register (SCFCR2) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): 16.2.11 Serial Port 750, 751 Description amended Register (SCSPTR2) 17.1 Overview 775 17.1.3 Pin ...
Page 30
Item Page 19.1.2 Block Diagram 826 Figure 19.1 Block Diagram of INTC 19.1.3 Pin 827 Configuration Table 19.1 INTC Pins 19.2.1 NMI Interrupt 828 19.2.2 IRL Interrupts 830 19.2.3 On-Chip 831 Peripheral Module Interrupts Rev.7.00 Oct. 10, 2008 Page xxviii ...
Page 31
Item Page 19.4.1 Interrupt 843 Operation Sequence Figure 19.3 Interrupt 844 Operation Flowchart 19.6 Usage Notes 847 to 849 Revision (See Manual for Details) Description and notes amended 3. The priority level of the interrupt selected by the interrupt controller ...
Page 32
Item Page 20.2.1 Access to UBC 854 Control Registers 21.1.1 Features 879 21.1.3 Pin 881, 882 Note amended Configuration Table 21.1 H-UDI Pins Rev.7.00 Oct. 10, 2008 Page xxx of lxxxiv REJ09B0366-0700 Revision (See Manual for Details) Description amended 2. ...
Page 33
Item Page 21.2.5 Boundary Scan 887 Register (SDBSR) (SH7750R Only) Table 21.3 888 Configuration of the Boundary Scan Register 890 21.3.4 Boundary Scan 893 (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) 21.4 Usage Notes 894 Revision (See Manual for Details) Description amended ...
Page 34
Item Page Section 22 Electrical 895 to Characteristics 1016 22.1 Absolute 895 Maximum Ratings Table 22.1 Absolute Maximum Ratings 22.2 DC 896, 897 Title and table amended Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) Table 22.3 DC 899 ...
Page 35
Item Page 22.2 DC 900, 901 Title and table amended Characteristics Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) Table 22.5 DC 903 Characteristics (HD6417750RF200 (V)) Table 22.6 DC 904 Characteristics (HD6417750SBP200 (V)) Table 22.7 DC 906 Characteristics (HD6417750SF200 (V)) ...
Page 36
Item Page 22.2 DC 912 Characteristics Table 22.10 DC Characteristics (HD6417750F167 (V)) Table 22.12 DC — Characteristics (HD6417750F167I (V)) Table 22.11 DC 914 Characteristics (HD6417750SVF133 (V)) Table 22.12 DC 916 Characteristics (HD6417750SVBT133 (V)) Table 22.13 DC 918 Characteristics (HD6417750VF128 (V)) ...
Page 37
Item Page 22.3 AC 920 Characteristics Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V)) Table 22.20 Clock 921 Timing (HD6417750F167 (V), HD6417750SF167 (V) ) 22.3.1 Clock and 922 Control Signal Timing Table 22.23 Clock and Control ...
Page 38
Item Page 22.3.1 Clock and 936, 937 Description and notes amended Control Signal Timing Table 22.30 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133 (V)) Table 22.31 Clock and 939 Control Signal Timing (HD6417750VF128) Figure 22.11 Manual 945 Reset Input Timing ...
Page 39
Item Page 22.3.2 Control Signal 947 Timing Table 22.32 Control Signal Timing (2) Figure 22.14 (1) Pin 948 Drive Timing for Reset or Sleep Mode Figure 22.14 (2) Pin 949 Drive Timing for Software Standby Mode 22.3.3 Bus Timing 950, ...
Page 40
Item Page 22.3.3 Bus Timing 952, 953 Table and notes amended Table 22.33 Bus Timing (2) Table 22.33 Bus 954, 955 Table and notes amended Timing (3) Rev.7.00 Oct. 10, 2008 Page xxxviii of lxxxiv REJ09B0366-0700 Revision (See Manual for ...
Page 41
Item Page 22.3.3 Bus Timing 966 Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) Figure 22.26 967 Synchronous DRAM Normal Read Bus Cycle: PRE + ...
Page 42
Item Page 22.3.3 Bus Timing 973 Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) Figure 22.52 PCMCIA 994 Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) ...
Page 43
Item Page 22.3.4 Peripheral 1007 Module Signal Timing Table 22.34 Peripheral Module Signal Timing (3) Table 22.34 Peripheral 1008, Module Signal Timing 1009 (4) Revision (See Manual for Details) Table and notes amended Module Item Symbol Notes: 1. Pcyc: P ...
Page 44
Item Page 22.3.4 Peripheral 1010 Module Signal Timing Table 22.34 Peripheral Module Signal Timing (5) Appendix A Address 1017 to List 1022 Table A.1 Address List ⎯ Appendix B Package Dimensions Figure B.2 Package Dimensions (256-Pin BGA) Figure B.4 Package ...
Page 45
Item Page E.1 Pin States 1033 Table E.1 Pin States in Reset, Power-Down State, and Bus- Released State Revision (See Manual for Details) Table and notes amended Reset (Power-On) Signal Name I/O Master Slave D0– D8–D15 ...
Page 46
Item Page E.1 Pin States 1034 Table E.1 Pin States in Reset, Power-Down State, and Bus- Released State 1035 Rev.7.00 Oct. 10, 2008 Page xliv of lxxxiv REJ09B0366-0700 Revision (See Manual for Details) Reset (Power-On) Signal Name I/O Master Slave ...
Page 47
Item Page E.1 Pin States 1035, 1036 Table E.1 Pin States in Reset, Power-Down State, and Bus- Released State Revision (See Manual for Details) PI: Input (Pulled Up) PZ: High-impedance (Pulled Up) Notes: 1. Output when area 2 is used ...
Page 48
Item Page E.2 Handling of 1036 Unused Pins Appendix F 1053 Synchronous DRAM Address Multiplexing Tables (17) BUS 64 (128 × × 4) × 8* (SH7750R only) Appendix H Power-On 1061 to and Power-Off 1063 ...
Page 49
Section 1 Overview ............................................................................................................. 1.1 SH7750, SH7750S, SH7750R Groups Features ............................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement ............................................................................................................... 10 1.4 Pin Functions .................................................................................................................... 14 1.4.1 Pin Functions (256-Pin BGA).............................................................................. 14 1.4.2 Pin Functions (208-Pin QFP)............................................................................... 24 1.4.3 Pin Functions ...
Page 50
Single Virtual Memory Mode and Multiple Virtual Memory Mode ................... 85 3.3.7 Address Space Identifier (ASID) ......................................................................... 85 3.4 TLB Functions .................................................................................................................. 86 3.4.1 Unified TLB (UTLB) Configuration ................................................................... 86 3.4.2 Instruction TLB (ITLB) Configuration................................................................ 90 3.4.3 Address Translation ...
Page 51
RAM Mode .......................................................................................................... 123 4.3.7 OC Index Mode.................................................................................................... 124 4.3.8 Coherency between Cache and External Memory ............................................... 125 4.3.9 Prefetch Operation ............................................................................................... 125 4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)................................... 125 4.4 Instruction Cache (IC)....................................................................................................... 128 4.4.1 ...
Page 52
Exception Requests and BL Bit ........................................................................... 158 5.5.4 Return from Exception Handling......................................................................... 158 5.6 Description of Exceptions................................................................................................. 158 5.6.1 Resets................................................................................................................... 159 5.6.2 General Exceptions .............................................................................................. 164 5.6.3 Interrupts.............................................................................................................. 178 5.6.4 Priority Order with Multiple Exceptions.............................................................. 181 5.7 Usage Notes ...
Page 53
Section 8 Pipelining ............................................................................................................ 231 8.1 Pipelines............................................................................................................................ 231 8.2 Parallel-Executability........................................................................................................ 238 8.3 Execution Cycles and Pipeline Stalling ............................................................................ 242 8.4 Usage Notes ...................................................................................................................... 258 Section 9 Power-Down Modes 9.1 Overview........................................................................................................................... 259 9.1.1 Types of Power-Down Modes ............................................................................. 259 9.1.2 Register ...
Page 54
Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 283 9.9 Usage Notes ...................................................................................................................... 286 9.9.1 Note on Current Consumption ............................................................................. 286 Section 10 Clock Oscillation Circuits 10.1 Overview........................................................................................................................... 287 10.1.1 Features................................................................................................................ 287 10.2 Overview of CPG.............................................................................................................. 289 10.2.1 Block ...
Page 55
Block Diagram ..................................................................................................... 312 11.1.3 Pin Configuration................................................................................................. 313 11.1.4 Register Configuration......................................................................................... 313 11.2 Register Descriptions ........................................................................................................ 315 11.2 Counter (R64CNT).................................................................................... 315 11.2.2 Second Counter (RSECCNT) .............................................................................. 316 11.2.3 Minute Counter (RMINCNT) .............................................................................. 316 11.2.4 Hour Counter (RHRCNT).................................................................................... ...
Page 56
Timer Output Control Register (TOCR) .............................................................. 341 12.2.2 Timer Start Register (TSTR) ............................................................................... 342 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) .............................................. 343 12.2.4 Timer Constant Registers (TCOR) ...................................................................... 344 12.2.5 Timer Counters (TCNT) ...................................................................................... 344 12.2.6 Timer ...
Page 57
Refresh Count Register (RFCR) .......................................................................... 420 13.2.15 Notes on Accessing Refresh Control Registers.................................................... 420 13.3 Operation........................................................................................................................... 421 13.3.1 Endian/Access Size and Data Alignment............................................................. 421 13.3.2 Areas .................................................................................................................... 433 13.3.3 SRAM Interface ................................................................................................... 438 13.3.4 DRAM Interface .................................................................................................. 447 13.3.5 ...
Page 58
Examples of Transfer between External Memory and an External Device with DACK .................................................................................................................. 602 14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 603 14.5.1 Operation ............................................................................................................. 603 14.5.2 Pins in DDT Mode............................................................................................... 605 14.5.3 Transfer Request Acceptance on Each Channel ...
Page 59
Bit Rate Register (SCBRR1)................................................................................ 676 15.3 Operation........................................................................................................................... 684 15.3.1 Overview.............................................................................................................. 684 15.3.2 Operation in Asynchronous Mode ....................................................................... 686 15.3.3 Multiprocessor Communication Function............................................................ 698 15.3.4 Operation in Synchronous Mode ......................................................................... 707 15.4 SCI Interrupt Sources and DMAC .................................................................................... 717 15.5 ...
Page 60
Register Descriptions ........................................................................................................ 778 17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 778 17.2.2 Serial Mode Register (SCSMR1)......................................................................... 779 17.2.3 Serial Control Register (SCSCR1)....................................................................... 780 17.2.4 Serial Status Register (SCSSR1).......................................................................... 781 17.3 Operation .......................................................................................................................... 782 17.3.1 Overview.............................................................................................................. 782 17.3.2 Pin ...
Page 61
Register Descriptions ........................................................................................................ 835 19.3.1 Interrupt Priority Registers (IPRA–IPRD) ............................................... 835 19.3.2 Interrupt Control Register (ICR).......................................................................... 837 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)........ 839 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only).............................. 840 19.3.5 ...
Page 62
Condition Match Flag Setting .............................................................................. 868 20.3.7 Program Counter (PC) Value Saved .................................................................... 868 20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 869 20.3.9 Usage Notes ......................................................................................................... 870 20.4 User Break Debug Support Function ................................................................................ 872 20.5 ...
Page 63
Delay Time Variation Due to Load Capacitance ............................................... 1016 Appendix A Address List Appendix B Package Dimensions Appendix C Mode Pin Settings Appendix D CKIO2ENB Pin Configuration Appendix E Pin Functions E.1 Pin States......................................................................................................................... 1033 E.2 Handling of Unused ...
Page 64
Rev.7.00 Oct. 10, 2008 Page lxii of lxxxiv REJ09B0366-0700 ...
Page 65
Section 1 Overview Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions ........................ Figure 1.2 Pin Arrangement (256-Pin BGA)........................................................................... 10 Figure 1.3 Pin Arrangement (208-Pin QFP) ............................................................................ 11 Figure 1.4 Pin Arrangement (264-Pin CSP) ............................................................................ 12 Figure 1.5 Pin Arrangement (292-Pin ...
Page 66
Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S).......................................... 117 Figure 4.3 Configuration of Operand Cache (SH7750R) ........................................................ 118 Figure 4.4 Configuration of Write-Back Buffer ...................................................................... 122 Figure 4.5 Configuration of Write-Through Buffer................................................................. 122 Figure 4.6 Configuration of Instruction Cache (SH7750, ...
Page 67
STATUS Output in Sleep → Manual Reset Sequence........................................... 280 Figure 9.8 STATUS Output in Deep Sleep → Interrupt Sequence ......................................... 281 Figure 9.9 Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ............................. 281 Figure 9.11 STATUS Output ...
Page 68
Figure 13.6 Basic Timing of SRAM Interface........................................................................... 439 Figure 13.7 Example of 64-Bit Data Width SRAM Connection ............................................... 440 Figure 13.8 Example of 32-Bit Data Width SRAM Connection ............................................... 441 Figure 13.9 Example of 16-Bit Data Width SRAM Connection ............................................... ...
Page 69
Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle.................................................................................................... 483 Figure 13.39 Auto-Refresh Operation ......................................................................................... 485 Figure 13.40 Synchronous DRAM Auto-Refresh Timing........................................................... 486 Figure 13.41 Synchronous DRAM Self-Refresh Timing ............................................................ 487 Figure 13.42 ...
Page 70
Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 521 Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait ...
Page 71
Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) ................................................................ 590 Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ................................................................. 591 Figure 14.16 Dual Address ...
Page 72
Figure 14.35 Read from Synchronous DRAM Precharge Bank.................................................. 618 Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ...................... 618 Figure 14.37 Read from Synchronous DRAM (Row Hit) ........................................................... 619 Figure 14.38 Write to Synchronous DRAM Precharge Bank...................................................... 619 ...
Page 73
Section 15 Serial Communication Interface (SCI) Figure 15.1 Block Diagram of SCI............................................................................................ 657 Figure 15.2 MD0/SCK Pin ........................................................................................................ 674 Figure 15.3 MD7/TxD Pin......................................................................................................... 675 Figure 15.4 RxD Pin.................................................................................................................. 675 Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, ...
Page 74
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 Block Diagram of SCIF.......................................................................................... 727 Figure 16.2 MD8/RTS2 Pin....................................................................................................... 753 Figure 16.3 CTS2 Pin ................................................................................................................ 754 Figure 16.4 MD1/TxD2 Pin....................................................................................................... 755 Figure 16.5 MD2/RxD2 Pin ...................................................................................................... 755 Figure 16.6 Sample ...
Page 75
Figure 18.6 MD1/TxD2 Pin....................................................................................................... 808 Figure 18.7 MD2/RxD2 Pin ...................................................................................................... 808 Figure 18.8 CTS2 Pin ................................................................................................................ 809 Figure 18.9 MD8/RTS2 Pin....................................................................................................... 810 Section 19 Interrupt Controller (INTC) Figure 19.1 Block Diagram of INTC......................................................................................... 826 Figure 19.2 Example of IRL Interrupt ...
Page 76
Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ................................................................................. 959 Figure 22.19 Burst ROM Bus Cycle (No Wait) .......................................................................... 960 Figure 22.20 Burst ROM Bus Cycle (1st Data: ...
Page 77
Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................................................................................................... 980 Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................................................................................................... 981 Figure 22.40 DRAM ...
Page 78
Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) ................................ 1000 Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic ...
Page 79
Section 1 Overview Table 1.1 LSI Features ........................................................................................................... Table 1.2 Pin Functions.......................................................................................................... 14 Table 1.3 Pin Functions.......................................................................................................... 24 Table 1.4 Pin Functions.......................................................................................................... 32 Table 1.5 Pin Functions.......................................................................................................... 42 Section 2 Programming Model Table 2.1 Initial Register Values ............................................................................................ 55 Section ...
Page 80
Table 7.3 Fixed-Point Transfer Instructions........................................................................... 216 Table 7.4 Arithmetic Operation Instructions.......................................................................... 218 Table 7.5 Logic Operation Instructions.................................................................................. 220 Table 7.6 Shift Instructions .................................................................................................... 221 Table 7.7 Branch Instructions ................................................................................................ 222 Table 7.8 System Control Instructions ................................................................................... 223 Table 7.9 Floating-Point ...
Page 81
Section 13 Bus State Controller (BSC) Table 13.1 BSC Pins ................................................................................................................ 360 Table 13.2 BSC Registers ........................................................................................................ 364 Table 13.3 External Memory Space Map................................................................................. 366 Table 13.4 PCMCIA Interface Features ................................................................................... 368 Table 13.5 PCMCIA Support Interfaces .................................................................................. 369 Table ...
Page 82
Table 14.16 Function of BAVL ................................................................................................. 648 Table 14.17 DTR Format for Clearing Request Queues ............................................................ 649 Table 14.18 DMAC Interrupt-Request Codes............................................................................ 650 Section 15 Serial Communication Interface (SCI) Table 15.1 SCI Pins.................................................................................................................. 658 Table 15.2 SCI Registers.......................................................................................................... 659 Table ...
Page 83
Section 18 I/O Ports Table 18.1 20-Bit General-Purpose I/O Port Pins .................................................................... 811 Table 18.2 SCI I/O Port Pins.................................................................................................... 812 Table 18.3 SCIF I/O Port Pins.................................................................................................. 812 Table 18.4 I/O Port Registers ................................................................................................... 813 Section 19 Interrupt Controller (INTC) Table ...
Page 84
Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) .................... 920 Table 22.16 Clock Timing (HD6417750RF240 (V))................................................................. 920 Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V))............................................. 920 Table 22.18 Clock Timing (HD6417750RF200 (V))................................................................. 920 Table 22.19 Clock ...
Page 85
Appendix I Product Lineup Table I.1 SH7750/SH7750S/SH7750R Product Lineup ...................................................... 1065 Appendix J Version Registers Table J.1 Register Configuration ......................................................................................... 1067 Rev.7.00 Oct. 10, 2008 Page lxxxiii of lxxxiv REJ09B0366-0700 ...
Page 86
Rev.7.00 Oct. 10, 2008 Page lxxxiv of lxxxiv REJ09B0366-0700 ...
Page 87
SH7750, SH7750S, SH7750R Groups Features This LSI (SH7750, SH7750S, and SH7750R Groups 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction ...
Page 88
Section 1 Overview Item Features • CPU Renesas Technology original SuperH architecture • 32-bit internal data bus • General register file: ⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system ...
Page 89
Item Features • FPU On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation ...
Page 90
Section 1 Overview Item Features • Clock pulse Choice of main clock: generator (CPG) ⎯ SH7750, SH7750S: 1/ times EXTAL ⎯ SH7750R times EXTAL • Clock modes: ⎯ CPU frequency: 1, 1/2, ...
Page 91
Item Features • Cache memory Instruction cache (IC) [SH7750, SH7750S] ⎯ 8 Kbytes, direct mapping ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯ 512 ...
Page 92
Section 1 Overview Item Features • Interrupt controller Five independent external interrupts: NMI, IRL3 to IRL0 (INTC) • 15-level encoded external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module • User ...
Page 93
Item Features • Direct memory Physical address DMA controller: access controller ⎯ SH7750, SH7750S: 4-channel (DMAC) ⎯ SH7750R: 8-channel • Transfer data size: 8, 16, 32 bits bytes • Address modes: ⎯ Single address mode ⎯ ...
Page 94
Section 1 Overview Item Features Product lineup Abbre- viation SH7750 SH7750S SH7750R Rev.7.00 Oct. 10, 2008 Page 8 of 1074 REJ09B0366-0700 Voltage Operating (Internal) Frequency Model No. 1.95 V 200 MHz HD6417750BP200M 1.8 V 167 MHz HD6417750F167 1.5 V 128 ...
Page 95
Block Diagram Figure 1.1 shows an internal block diagram of this LSI. I cache CPG INTC SCI (SCIF) RTC TMU Legend: BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller FPU: Floating-point unit INTC: Interrupt ...
Page 96
Section 1 Overview 1.3 Pin Arrangement RDY RESET B CS0 CS1 C CS6 BS D D47 D32 E D46 D33 F D45 RD2 D34 G D44 D35 H D43 D36 J D42 D37 K ...
Page 97
RDY 1 RESET 2 CS0 3 CS1 4 CS4 5 CS5 6 CS6 D47 11 D32 D46 15 16 D33 D45 17 D34 18 D44 19 20 D35 21 22 D43 23 ...
Page 98
Section 1 Overview VSS-CPG XTAL EXTAL VDD-CPG B RESET CS4 C RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK D CS0 VSSQ E BS CS1 CS5 CS6 F RD2 VDD D47 VDDQ G D45 VDDQ D46 VSS H ...
Page 99
A RDY RESET B CS0 CS1 C CS5 CS6 D RD2 D47 E D32 CS4 D46 F D33 BS D45 G D34 D44 H D35 D43 J D36 D42 D37 K D38 L D41 ...
Page 100
Section 1 Overview 1.4 Pin Functions 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions Pin No. No. Pin Name I/O RDY RESET CS0 CS1 CS4 5 D4 ...
Page 101
Pin No. No. Pin Name I D43 I D36 I D42 I D37 I VDDQ Power IO VDD (3 VSSQ Power IO GND ( ...
Page 102
Section 1 Overview Pin No. No. Pin Name I I/O BACK BSREQ BREQ BSACK I I CKE VDDQ Power IO ...
Page 103
Pin No. No. Pin Name I A10 VDDQ Power IO VDD (3 VSSQ Power IO GND ( W10 Y10 Y11 ...
Page 104
Section 1 Overview Pin No. No. Pin Name I/O WE2/CAS2/ 116 Y17 O DQM2/ ICIORD WE3/CAS3/ 117 W17 O DQM3/ ICIOWR WE6/CAS6/ 118 Y18 O DQM6 119 V16 VDDQ Power IO VDD (3.3 V) 120 U16 VSSQ Power IO GND ...
Page 105
Pin No. No. Pin Name I/O 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 D17 I/O 146 P20 D30 I/O 147 N19 D16 I/O 148 N20 D31 I/O 149 M18 ...
Page 106
Section 1 Overview Pin No. No. Pin Name I/O 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 E18 RD/WR2 O 179 D20 MD0/SCK I/O 180 D19 MD1/TXD2 I/O 181 D18 MD2/RXD2 ...
Page 107
Pin No. No. Pin Name I/O 200 A16 SCK2/ I MRESET 201 C14 VDD Power Internal VDD 202 D14 VSS Power Internal GND 203 A15 A18 O 204 B14 A19 O 205 C13 VDDQ Power IO VDD (3.3 V) 206 ...
Page 108
Section 1 Overview Pin No. No. Pin Name I/O 228 A7 MD6/ I IOIS16 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power IO GND (0 V) ASEBRK/ 231 B7 I/O BRKACK 232 A6 TDO O 233 ...
Page 109
Pin No. No. Pin Name I/O 250 D16 NC 251 H17 NC 252 H18 NC 253 N3 NC 254 N4 NC 255 U4 NC 256 V18 NC Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power ...
Page 110
Section 1 Overview 1.4.2 Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Pin No. Pin Name I/O Function RDY 1 I Bus ready RESET 2 I Reset CS0 3 O Chip select 0 CS1 4 O Chip select 1 CS4 ...
Page 111
Pin No. Pin Name I/O Function 30 D39 I/O Data/port 31 VDDQ Power IO VDD (3 VSSQ Power IO GND ( D15 I/O Data 34 D0 I/O Data 35 D14 I/O Data 36 D1 I/O Data ...
Page 112
Section 1 Overview Pin No. Pin Name I/O Function WE5/CAS5 D47–D40 select DQM5 signal WE4/CAS4 D39–D32 select DQM4 signal WE1/CAS1 D15–D8 select DQM1 signal WE0/CAS0 D7–D0 select DQM0 signal 62 A17 O ...
Page 113
Pin No. Pin Name I/O Function 86 DRAK0 O DMAC0 request acknowledge 87 VDDQ Power IO VDD (3 VSSQ Power IO GND (0 V) CS3 89 O Chip select 3 CS2 90 O Chip select 2 91 VDD ...
Page 114
Section 1 Overview Pin No. Pin Name I/O Function 112 D27 I/O Data 113 VDDQ Power IO VDD (3.3 V) 114 VSSQ Power IO GND (0 V) 115 D19 I/O Data 116 D28 I/O Data 117 VDD Power Internal VDD ...
Page 115
Pin No. Pin Name I/O Function 144 VSS Power Internal GND (0 V) 145 D48 I/O Data/port 146 D63 I/O Data 147 VDDQ Power IO VDD (3.3 V) 148 VSSQ Power IO GND (0 V) 149 MD0/SCK I/O Mode/SCI clock ...
Page 116
Section 1 Overview Pin No. Pin Name I/O Function 168 SCK2/ I SCIF clock/ MRESET manual reset 169 VDD Power Internal VDD 170 VSS Power Internal GND (0 V) 171 A18 O Address 172 A19 O Address 173 A20 O ...
Page 117
Pin No. Pin Name I/O Function 194 TDO O Data out (H-UDI) 195 VDD Power Internal VDD 196 VSS Power Internal GND (0 V) 197 TMS I Mode (H-UDI) 198 TCK I Clock (H-UDI) 199 TDI I Data in (H-UDI) ...
Page 118
Section 1 Overview 1.4.3 Pin Functions (264-Pin CSP) Table 1.4 Pin Functions Pin No. No. Pin Name I/O RDY RESET CS0 CS1 CS4 CS5 6 ...
Page 119
Pin No. No. Pin Name I D37 I VDDQ Power IO VDD (3 VSSQ Power IO GND ( D41 I D38 I D40 I ...
Page 120
Section 1 Overview Pin No. No. Pin Name I/O BACK BSREQ BREQ BSACK I I CKE VDDQ Power IO VDD (3 ...
Page 121
Pin No. No. Pin Name I VSSQ Power IO GND ( CKIO VDDQ Power IO VDD (3 ...
Page 122
Section 1 Overview Pin No. No. Pin Name I/O 115 R13 WE3/CAS3/ O DQM3/ ICIOWR 116 R14 WE6/CAS6/ O DQM6 117 U14 VDDQ Power IO VDD (3.3 V) 118 U17 VSSQ Power IO GND (0 V) 119 U15 WE7/CAS7/ O ...
Page 123
Pin No. No. Pin Name I/O 143 L17 D17 I/O 144 L12 D30 I/O 145 K15 D16 I/O 146 K14 D31 I/O 147 K17 VDDQ Power IO VDD (3.3 V) 148 K13 VSSQ Power IO GND (0 V) 149 K16 ...
Page 124
Section 1 Overview Pin No. No. Pin Name I/O 175 E14 RD/WR2 O 176 F16 MD0/SCK I/O 177 C15 MD1/TXD2 I/O 178 E15 MD2/RXD2 I 179 D15 IRL0 I 180 D17 IRL1 I IRL2 181 A17 I IRL3 182 B17 ...
Page 125
Pin No. No. Pin Name I/O 198 D11 VSS Power Internal GND 199 C11 A18 O 200 F12 A19 O 201 B11 VDDQ Power IO VDD (3.3 V) 202 E11 VSSQ Power IO GND (0 V) 203 A11 A20 O ...
Page 126
Section 1 Overview Pin No. No. Pin Name I/O ASEBRK/ 227 E6 I/O BRKACK 228 A6 TDO O 229 D7 VDD Power Internal VDD 230 B7 VSS Power Internal GND 231 E5 TMS I 232 C6 TCK I 233 D6 ...
Page 127
Pin No. No. Pin Name I/O 256 M7 NC-13 257 N2 NC-14 258 P2 NC-15 259 P16 NC-16 260 R17 NC-17 261 T4 NC-18 262 T14 NC-19 263 U3 NC-20 264 U4 NC-21 Legend: I: Input O: Output I/O: Input/output ...
Page 128
Section 1 Overview 1.4.4 Pin Functions (292-Pin BGA) Table 1.5 Pin Functions Pin No. No. Pin Name I/O RDY RESET CS0 CS1 CS4 CS5 6 ...
Page 129
Pin No. No. Pin Name I D37 I VDDQ Power IO VDD (3 VSS Power GND ( D41 I D38 I D40 I D39 ...
Page 130
Section 1 Overview Pin No. No. Pin Name I/O BREQ BSACK I I CKE VDDQ Power IO VDD (3 VSS Power GND (0 ...
Page 131
Pin No. No. Pin Name I/O 91 W10 Y10 CKIO O 93 V10 VDDQ Power IO VDD (3 U10 VSS Power GND ( V11 CKIO2 O 96 W11 Y11 A5 ...
Page 132
Section 1 Overview Pin No. No. Pin Name I/O 119 V16 VDDQ Power IO VDD (3.3 V) 120 U16 VSS Power GND (0 V) WE7/CAS7/ 121 V18 O DQM7/REG 122 W18 D23 I/O 123 Y18 D24 I/O 124 Y19 D22 ...
Page 133
Pin No. No. Pin Name I/O 150 M17 VSS Power GND (0 V) 151 M19 D55 I/O 152 M20 D56 I/O 153 L19 D54 I/O 154 L20 D57 I/O 155 L18 VDDQ Power IO VDD (3.3 V) 156 L17 VSS ...
Page 134
Section 1 Overview Pin No. No. Pin Name I/O 182 D20 IRL0 I 183 C19 IRL1 I 184 C20 IRL2 I IRL3 185 B19 I 186 B20 NMI I 187 A20 XTAL2 O 188 A19 EXTAL2 I 189 B18 VSS-RTC ...
Page 135
Pin No. No. Pin Name I/O 210 A13 A23 O 211 C12 VDDQ Power IO VDD (3.3 V) 212 D12 VSS Power GND (0 V) 213 B12 A24 O 214 A12 A25 O 215 B11 MD3/CE2A I/O 216 A11 MD4/CE2B ...
Page 136
Section 1 Overview Pin No. No. Pin Name I/O TRST 238 B5 I CKIO2ENB I 239 C4 240 D6 VSS Power GND (0 V) 241 A5 VDD-PLL2 Power PLL2 VDD 242 B4 VSS-PLL2 Power PLL2 GND (0 V) 243 A4 ...
Page 137
Pin No. No. Pin Name I/O 269 L13 VSS Power GND (0 V) 270 K13 VSS Power GND (0 V) 271 J13 VSS Power GND (0 V) 272 H13 VSS Power GND (0 V) 273 H12 VSS Power GND (0 ...
Page 138
Section 1 Overview Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on- chip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. CKIO2 is ...
Page 139
Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH-4 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits) Double-precision floating-point (64 bits ...
Page 140
Section 2 Programming Model 2.2 Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception ...
Page 141
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or ...
Page 142
Section 2 Programming Model BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * ...
Page 143
General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one ...
Page 144
Section 2 Programming Model SR. (SR. SR. R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 Programming Note: ...
Page 145
Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and ...
Page 146
Section 2 Programming Model • Single-precision floating-point extended register pairs, XDi (8 registers register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, ...
Page 147
FPSCR. FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 DR6 FR6 FR7 FV8 DR8 FR8 FR9 DR10 FR10 FR11 FV12 DR12 FR12 FR13 DR14 FR14 FR15 XMTRX XD0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 ...
Page 148
Section 2 Programming Model 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined — Note: —: Reserved. These ...
Page 149
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The ...
Page 150
Section 2 Programming Model Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001 — Note: —: Reserved. These bits are always read as 0, and should only be written with 0. ...
Page 151
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set ...
Page 152
Section 2 Programming Model Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access ...
Page 153
Address A Byte 0 Byte 1 Byte 2 Byte 3 15 Address Word 0 31 Address Longword Big endian Note: The SH-4 does not support ...
Page 154
Section 2 Programming Model contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. ...
Page 155
Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to ...
Page 156
Section 2 Programming Model Rev.7.00 Oct. 10, 2008 Page 70 of 1074 REJ09B0366-0700 ...
Page 157
Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32- bit logical (virtual) address space. Address translation from virtual address to physical address is ...
Page 158
Section 3 Memory Management Unit (MMU) of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner also provided with memory protection functions to prevent a process from inadvertently accessing ...
Page 159
Physical Process 1 memory Process 1 Process 1 Process 2 Process 3 Section 3 Memory Management Unit (MMU) Process 1 Physical memory (1) Physical Process 1 memory Process 2 Process 3 (3) Figure 3.1 Role of the MMU Rev.7.00 Oct. ...
Page 160
Section 3 Memory Management Unit (MMU) 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Name tion Page table entry high PTEH register Page table entry low PTEL register Page table entry PTEA ...
Page 161
Register Descriptions There are six MMU-related registers. 1. PTEH 31 2. PTEL — — — 3. PTEA 31 4. TTB 31 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. ...
Page 162
Section 3 Memory Management Unit (MMU) 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number ...
Page 163
URC: UTLB replace counter SQMD: Store queue mode bit SV: Single virtual mode bit TI: TLB invalidate AT: Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area ...
Page 164
Section 3 Memory Management Unit (MMU) ITLB entry 0 is updated ITLB entry 1 is updated ITLB entry 2 is updated ITLB entry 3 is updated Other than the above Ensure that values for which “Setting prohibited” is indicated in ...
Page 165
MMU exceptions are not generated when the AT bit the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. 3.3 Address Space 3.3.1 Physical Address Space The SH-4 ...
Page 166
Section 3 Memory Management Unit (MMU) In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the ...
Page 167
H'E000 0000 H'E400 0000 H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000 H'FC00 0000 The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). ...
Page 168
Section 3 Memory Management Unit (MMU) The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data ...
Page 169
Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, ...
Page 170
Section 3 Memory Management Unit (MMU) 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Here, access to the PCMCIA ...
Page 171
Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical ...
Page 172
Section 3 Memory Management Unit (MMU) Note: In single virtual memory mode, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. 3.4 TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified ...
Page 173
Virtual address 31 VPN • 4-Kbyte page Virtual address VPN • 64-Kbyte page Virtual address VPN • 1-Mbyte page Virtual address VPN Figure 3.8 Relationship between Page Size ...
Page 174
Section 3 Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte ...
Page 175
C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear ...
Page 176
Section 3 Memory Management Unit (MMU) 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached ...
Page 177
Data access to virtual address (VA area in P2 area On-chip I/O access VPNs match and Data TLB miss exception PR R/W? R ...
Page 178
Section 3 Memory Management Unit (MMU area in P2 area 0 Access prohibited No Search UTLB Yes Match? No Instruction TLB miss exception Instruction TLB protection violation exception Figure 3.11 Flowchart of Memory Access ...
Page 179
MMU Functions 3.5.1 MMU Hardware Management The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. ...
Page 180
Section 3 Memory Management Unit (MMU) issued by a program in the area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR LRUI Entry specification PTEH ...
Page 181
ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or ...
Page 182
Section 3 Memory Management Unit (MMU) 3.6 MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB ...
Page 183
Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the ...
Page 184
Section 3 Memory Management Unit (MMU) 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, ...
Page 185
Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to ...
Page 186
Section 3 Memory Management Unit (MMU) Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order ...
Page 187
Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection ...
Page 188
Section 3 Memory Management Unit (MMU) Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to ...
Page 189
ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field ...
Page 190
Section 3 Memory Management Unit (MMU) 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading ...
Page 191
ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data ...
Page 192
Section 3 Memory Management Unit (MMU) 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or ...
Page 193
Address field Data field Legend: VPN: Virtual page number V: Validity bit E: Entry D: Dirty bit Figure 3.16 Memory-Mapped UTLB Address Array 3.7.5 UTLB Data Array ...
Page 194
Section 3 Memory Management Unit (MMU) 31 Address field Data field Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits D: Dirty ...
Page 195
Address field Data field Legend: TC: Timing control bit E: Entry Figure 3.18 Memory-Mapped UTLB Data Array 2 3.8 Usage Notes 1. Address Space Identifier (ASID) in Single Virtual ...
Page 196
Section 3 Memory Management Unit (MMU) Rev.7.00 Oct. 10, 2008 Page 110 of 1074 REJ09B0366-0700 ...
Page 197
Overview 4.1.1 Features An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16- Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may alternatively be used as ...
Page 198
Section 4 Caches Table 4.2 Cache Features (SH7750R) Item Instruction Cache Capacity 16-Kbyte cache Type 2-way set-associative Line size 32 bytes Entries 256 entries/way Write method Replacement method LRU (least-recently-used) algorithm LRU algorithm Table 4.3 Features of Store Queues Item ...
Page 199
Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Cache Control Registers Name Abbreviation R/W Cache control CCR register Queue address QACR0 control register 0 Queue address QACR1 control register 1 Notes: 1. The initial value is ...
Page 200
Section 4 Caches 4.2 Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 EMODE * QACR0 31 QACR1 31 Notes: indicates reserved bits: 0 must be specified in a ...