HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet
HD6417760BL200AV
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HD6417760BL200AV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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... The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7760 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7750 Series SH7760 HD6417760BL200A HD6417760BL200AV HD6417760BL200AD HD6417760BL200ADV HD6417760BP200AD HD6417760BP200ADV Rev.2.00 2010.02 ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev. 2.00 Feb. 12, 2010 Page iv of lxxxii REJ09B0554-0200 ...
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The SH7760 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI ...
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Rev. 2.00 Feb. 12, 2010 Page vi of lxxxii REJ09B0554-0200 ...
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... Figure title amended Description amended Table 1.2 lists the pin configuration of the BP-256F (21 mm* and table 1.3 lists the pin configuration of the BP-256B (17 2 mm* ). Notes added Notes: 1. HD6417760BP200AD, HD6417760BP200ADV 2. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD, HD6417760BL200ADV Rev. 2.00 Feb. 12, 2010 Page vii of lxxxii 16 × 2 banks 1 ), REJ09B0554-0200 ...
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... Notes: 1. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD, HD6417760BL200ADV 2. HD6417760BP200AD, HD6417760BP200ADV Pin No mm* 21 mm* Function Pin Name Notes added Notes: 1. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD, HD6417760BL200ADV 2. HD6417760BP200AD, HD6417760BP200ADV Table amended Type Registers Control registers SR Description amended • Designed to meet IEEE754 standard Description amended The definitions in this section may not be applied to the SH-4 products other than the SH7760 ...
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Item Page 6.2.3 Page Table 124 Entry Assistance Register (PTEA) 7.3.9 Note on Using 164 to Cache Enhanced Mode 166 8.5.1 Resets 195 (1) Power-On Reset (2) Manual Reset 196 (3) H-UDI Reset 197 (4) Instruction TLB 198 Multiple-Hit Exception ...
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Item Page 9.4.5 Interrupt 242 Exception Handling and Priority Table 9.7 Interrupt Exception Handling Sources and Priority Order 10.5 Register 259 Descriptions Table 10.6 Register Configuration (2) 10.5.5 Wait Control 273 Register 1 (WCR1) Table 10.7 Idle Insertion between Accesses ...
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Item Page 10.5.8 Wait Control 282 Register 4 (WCR4) 283 Table 10.9 WCR3 and WCR4 Settings for Area 1 10.5.9 Memory 285 Control Register (MCR) 10.5.12 Refresh Timer 294 Control/Status Register (RTCSR) 10.6.2 Areas 308 (5) Area 4 Revision (See ...
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Item Page 11.3.4 DMA Channel 396 Control Register (CHCR) 11.4.4 Types of DMA 432 Transfer Figure 11.6 Data Flow in Single Address Mode 11.4.5 Number of Bus 460 Cycles and DREQ Pin Sampling Timing Figure 11.30 Single Address Mode/Burst Mode ...
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Item Page 11.6.2 DMABRG 468 Reset 11.6.5 DMA Audio 471 Transmit Operation Figure 11.32 Example of HAC DMA Transfer Operation Flow 11.6.11 LCDC DMA 478 Transfer Figure 11.38 Example of LCDC Data Transfer Flow 12.3 Clock Operating 491 Modes Table ...
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Item Page 15.3 Register 536 Descriptions Table 15.2 Register Configuration (2) 15.6.3 External Clock 545 Frequency 16.3.4 IRQ Status 557 Register (CMTIRQS) 16.4.4 16-Bit Timer: 562 Input Capture 16.4.5 16-Bit Timer: 563 Output Compare 16.4.7 Counter: Up- 565 Counter with ...
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Item Page 17.3 Register 574 Descriptions Table 17.2 Register Configuration (1) 575 17.3.14 Serial Error 601 Register (SCRER) 17.6 Usage Notes 626 (7) Notes on the TEND Flag 19.3.1 Slave Control 667 Register (ICSCR) Revision (See Manual for Details) Table ...
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Item Page 19.3.5 Master Control 674 Register (ICMCR) 19.3.6 Master Status 676 Register (ICMSR) 19.3.14 Receive FIFO 687 Data Count Register (ICRFDR) 19.3.15 Transmit FIFO 687 Data Count Register (ICTFDR) Rev. 2.00 Feb. 12, 2010 Page xvi of lxxxii REJ09B0554-0200 ...
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Item Page 19.4.8 Master 693 Transmit Operation (Single Buffer Mode) 19.5.1 Master 697, 698 Description amended Transmitter Operation (FIFO Buffer Mode) 19.6.1 Master 699 Transmitter (Single Buffer Mode) (4) Monitor the progress of data byte transmission: 19.6.4 Master 702 Transmitter ...
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Item Page 19.6.5 Master 703 Receiver (FIFO Buffer Mode) 19.7.1 Restriction 1 703, 704 Description replaced 19.7.2 Restriction 2 704, 705 Description replaced 20.3 Register 709 Descriptions Table 20.2 Register Configuration (1) 20.3.1 Control 711 Register (SSICR) 713 Rev. 2.00 ...
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Item Page 20.3.1 Control 714 Register (SSICR) 715 20.3.2 Status Register 720 (SSISR) 20.3.3 Transmit Data 721 Register (SSITDR) Revision (See Manual for Details) Table amended Bit Bit Name Initial Value R/W 8 DEL 0 R/W Bit Bit Name Initial ...
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Item Page 20.4.1 Bus Format 722 Table 20.3 Bus Formats of SSI Module 20.4.2 Non- 727 Compressed Modes Figure 20.6 Multichannel Format (4 Channels, No Padding) Figure 20.7 Multichannel Format (6 Channels with High Padding) Figure 20.8 728 Multichannel Format ...
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Item Page 20.5.2 Notes on 742 Stopping SSI Module Slave Mode Operation Section 21 USB Host 743 Module (USB) 21.1 Features 743 21.4 Memory 782 21.5.1 Storage Format 783 of Transfer Data Revision (See Manual for Details) Newly added Description ...
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Item Page 21.5.1 Storage Format 783 of Transfer Data 22.5.4 Interrupt 818 Request Register (CANIRR) 819 22.5.5 Interrupt Mask 824 Register (CANIMR) Rev. 2.00 Feb. 12, 2010 Page xxii of lxxxii REJ09B0554-0200 Revision (See Manual for Details) Description amended The ...
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Item Page 22.6.2 HCAN2 Settings 841 Figure 22.5 Reset Sequence 22.6.4 Message 845 Reception Sequence Figure 22.8 Message Receive Sequence Revision (See Manual for Details) Figure amended Reset sequence Configuration mode 1 Power on/software reset* Clear MCR0 2 Clear all ...
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Item Page 22.7 Usage Notes 848 23.4.5 HSPI Software 864 Reset 24.1 Features 867 Table 24.1 Multiplexed 868 Pins Controlled by Port Control Registers 24.2.21 GPIO Interrupt 892 Control Register (GPIOIC) 24.2.35 Peripheral 905 Module Select Register (IPSELR) Rev. 2.00 ...
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Item Page 25.3.7 TX Status 920 Register (HACTSR) 25.5.5 Restrictions — Related to HACTCR.CMDAMT 25.5.5 Initialization 930 Sequence Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write Revision (See Manual for Details) Table amended 2 Bit Bit Name Initial Value ...
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Item Page 25.5.5 Initialization 932 Sequence Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (cont) 26.8 Usage Note 994 Section 28 User 1019 Debug Interface (H- UDI) Rev. 2.00 Feb. 12, 2010 Page xxvi of lxxxii REJ09B0554-0200 Revision (See ...
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Item Page Section 28 User 1020 Debug Interface (H- UDI) Figure 28.1 H-UDI Block Diagram 28.1 Input/Output Pins 1022 Table 28.1 Pin Configuration 29.1 Features 1039 29.3.2 A/D 1045 Control/Status Register (ADCSR) 1046 Revision (See Manual for Details) Figure amended ...
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Item Page 29.4.2 Multi Mode 1049 29.4.5 External 1055 Trigger Input Timing 29.7.5 Notice of the 1059 DMA transmission of A/D converter 29.7.6 Notice of Scan 1060, mode and Multi mode 1061 of A/D conversion 29.7.7 Notice of Multi 1061 ...
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Item Page 30.3 Register Configuration Table 30.2 Register Configuration (1) 30.3.10 LCDC 1080 Horizontal Character Number Register (LDHCNR) 30.3.17 LCDC Power 1088 Management Mode Register (LDPMMR) 30.4.6 Power Supply 1099 Control Sequence Processing Figure 30.4 Power- Supply Control Sequence and ...
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Item Page 32.2 Register Bits 1179 1180 33.1 Absolute 1225 Maximum Ratings Table 33.1 Absolute Maximum Ratings 33.2 DC 1226 Characteristics Table 33.2 DC Characteristics ( −20 to 75°C/−40 to 85°C) 1227 Rev. 2.00 Feb. 12, 2010 Page ...
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Item Page 33.2 DC 1227 Characteristics Table 33.2 DC Characteristics ( −20 to 75°C/−40 to 85°C) 33.3.1 Clock and 1229 Control Signal Timing Table 33.5 Clock and Control Signal Timing 33.3.2 Control Signal 1236 Timing Table 33.6 Control ...
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Item Page 33.3.7 SCIF Module 1274 Signal Timing Table 33.11 SCIF Module Signal Timing 33.3.8 H-UDI Module 1275 Signal Timing Table 33.12 H-UDI Module Signal Timing 33.3.9 CMT Module 1276 Signal Timing Table 33.13 CMT Module Signal Timing 33.3.10 HCAN2 ...
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Item Page 2 33.3. Electrical 1280 Characteristics 2 Table 33. Bus Interface Module Signal Timing 2 Table 33. 1280 Schmitt characteristics 33.3.13 HSPI Module 1282 Signal Timing Table 33.20 HSPI Module Signal Timing Figure ...
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Item Page 33.3.16 SIM Module 1290 Signal Timing Table 33.25 SIM Module Signal Timing 33.3.17 MMCIF 1290 Module Signal Timing Table 33.26 MMCIF Module Signal Timing Figure 33.78 MMCIF — Receive Timing (falling edge sampling) 33.3.18 LCDC Module 1292 Signal ...
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Item Page 33.5 AC Characteristic 1297 Test Conditions Figure 33.88 Output Load Circuit A. Package 1299 Dimensions Figure A.1 Package Dimensions (BP- 256F/BP-256FV) Figure A.2 Package 1300 Dimensions (BP- 256B/BP-256BV) B. Mode Pin Settings 1301 Table B.1 Clock Operating Modes ...
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Item Page C.2 Handling of 1312 Unused Pins F. Power-on and 1325 to Power-off Procedures 1327 G. Product Lineup 1328 All trademarks and registered trademarks are the property of their respective owners. Rev. 2.00 Feb. 12, 2010 Page xxxvi of ...
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Section 1 Overview...........................................................................................1 1.1 SH7760 Features .............................................................................................................. 1 1.2 Block Diagram ................................................................................................................. 10 1.3 Pin Arrangement .............................................................................................................. 11 1.4 Pin Description................................................................................................................. 13 1.5 Pin Function ..................................................................................................................... 31 Section 2 Programming Model .........................................................................39 2.1 Data Formats .................................................................................................................... 39 2.2 Register Descriptions ...
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Pair Single-Precision Data Transfer.................................................................... 62 3.7 Usage Notes ..................................................................................................................... 63 3.7.1 Rounding Mode and Underflow Flag ................................................................. 63 3.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction .................................... 64 3.7.3 Sign of Operation Result when Using FIPR or ...
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Instruction TLB Multiple Hit Exception............................................................. 137 6.5.2 Instruction TLB Miss Exception......................................................................... 137 6.5.3 Instruction TLB Protection Violation Exception ................................................ 138 6.5.4 Data TLB Multiple Hit Exception....................................................................... 139 6.5.5 Data TLB Miss Exception................................................................................... 140 6.5.6 Data TLB Protection Violation Exception ...
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OC Address Array .............................................................................................. 175 7.6.4 OC Data Array .................................................................................................... 177 7.6.5 Summary of Memory-Mapping of OC ............................................................... 178 7.7 Store Queues .................................................................................................................... 178 7.7.1 SQ Configuration................................................................................................ 178 7.7.2 Writing to SQ...................................................................................................... 179 7.7.3 Transfer to External Memory.............................................................................. 179 ...
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Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04) ..... 234 9.4 Interrupt Sources .............................................................................................................. 235 9.4.1 NMI Interrupt...................................................................................................... 235 9.4.2 IRQ Interrupts ..................................................................................................... 235 9.4.3 IRL Interrupts...................................................................................................... 235 9.4.4 Peripheral Module Interrupts .............................................................................. 237 9.4.5 Interrupt Exception Handling and ...
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MPX Interface..................................................................................................... 359 10.6.8 Byte Control SRAM Interface ............................................................................ 369 10.6.9 Waits between Access Cycles............................................................................. 374 10.6.10 Bus Arbitration ................................................................................................... 375 10.6.11 Bus Release and Acquire Sequences .................................................................. 377 10.7 Usage Notes ..................................................................................................................... 378 10.7.1 Refresh ................................................................................................................ 378 10.7.2 ...
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Examples of Transfer between External Memory and an External Device with DACK ................................................................................................................. 465 11.6 DMABRG Operation ....................................................................................................... 467 11.6.1 DMABRG Request ............................................................................................. 467 11.6.2 DMABRG Reset ................................................................................................. 467 11.6.3 DMA Transfer Operating Mode for HAC and SSI ............................................. ...
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Watchdog Timer Counter (WTCNT).................................................................. 505 13.2.2 Watchdog Timer Control/Status Register (WTCSR).......................................... 505 13.2.3 Notes on Register Access.................................................................................... 507 13.3 Operation ......................................................................................................................... 507 13.3.1 Standby Clearing Procedure ............................................................................... 507 13.3.2 Frequency Changing Procedure .......................................................................... 508 13.3.3 Using Watchdog Timer Mode............................................................................. ...
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Reading from TCNT ........................................................................................... 545 15.6.3 External Clock Frequency................................................................................... 545 Section 16 Compare Match Timer (CMT)........................................................547 16.1 Features ............................................................................................................................ 547 16.2 Input/Output Pins ............................................................................................................. 548 16.3 Register Descriptions ....................................................................................................... 548 16.3.1 Configuration Register (CMTCFG) .................................................................... 550 16.3.2 Free-Running Timer ...
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Serial Port Register (SCSPTR) ........................................................................... 597 17.3.13 Line Status Register (SCLSR) ............................................................................ 600 17.3.14 Serial Error Register (SCRER) ........................................................................... 601 17.4 Operation ......................................................................................................................... 602 17.4.1 Overview............................................................................................................. 602 17.4.2 Operation in Asynchronous Mode ...................................................................... 604 17.4.3 Operation in Synchronous Mode ...
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Section Bus Interface .............................................................................663 19.1 Features ............................................................................................................................ 663 19.2 Input/Output Pins ............................................................................................................. 664 19.3 Register Descriptions ....................................................................................................... 664 19.3.1 Slave Control Register (ICSCR) ......................................................................... 667 19.3.2 Slave Status Register (ICSSR) ............................................................................ 668 19.3.3 Slave Interrupt Enable ...
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Restriction 2........................................................................................................ 704 Section 20 Serial Sound Interface (SSI) Module ............................................. 707 20.1 Features............................................................................................................................ 707 20.2 Input/Output Pins ............................................................................................................. 708 20.3 Register Descriptions ....................................................................................................... 709 20.3.1 Control Register (SSICR) ................................................................................... 710 20.3.2 Status Register (SSISR) ...................................................................................... 716 20.3.3 Transmit ...
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Periodic Start Register (HcPeriodicStart) ........................................................... 766 21.3.18 Low Speed Threshold Register (HcLSThreshold) .............................................. 767 21.3.19 Root Hub Descriptor A Register (HcRhDescriptorA) ........................................ 768 21.3.20 Root Hub Descriptor B Register (HcRhDescriptorB) ......................................... 770 21.3.21 Root Hub Status Register (HcRhStatus) ............................................................. ...
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Test Mode Settings ............................................................................................. 840 22.6.2 HCAN2 Settings ................................................................................................. 841 22.6.3 Message Transmission Sequence........................................................................ 842 22.6.4 Message Reception Sequence ............................................................................. 845 22.6.5 Reconfiguration of Mailbox................................................................................ 846 22.6.6 Standby Mode ..................................................................................................... 848 22.7 Usage Notes ..................................................................................................................... 848 22.7.1 Auto-Acknowledge Mode ...
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Port A Data Register (PADR) ............................................................................. 885 24.2.12 Port B Data Register (PBDR) ............................................................................. 886 24.2.13 Port C Data Register (PCDR) ............................................................................. 887 24.2.14 Port D Data Register (PDDR) ............................................................................. 887 24.2.15 Port E Data Register (PEDR).............................................................................. 888 24.2.16 ...
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AC 97 Frame Slot Structure............................................................................................. 926 25.5 Operation ......................................................................................................................... 927 25.5.1 Receiver .............................................................................................................. 927 25.5.2 Transmitter.......................................................................................................... 928 25.5.3 DMA ................................................................................................................... 928 25.5.4 Interrupts............................................................................................................. 928 25.5.5 Initialization Sequence........................................................................................ 929 25.5.6 Power-Down Mode............................................................................................. 934 25.5.7 Notes ................................................................................................................... 934 25.5.8 Reference ............................................................................................................ ...
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Notice about The MMCIF transfer data block size in multiblock read command............................................................................................................. 994 Section 27 Multifunctional Interface (MFI) .....................................................997 27.1 Features ............................................................................................................................ 997 27.2 Input/Output Pins ............................................................................................................. 999 27.3 Register Descriptions ....................................................................................................... 1000 27.3.1 MFI Index Register (MFIIDX) ........................................................................... ...
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Section 29 A/D Converter (ADC) ...................................................................1039 29.1 Features............................................................................................................................ 1039 29.2 Input/Output Pins ............................................................................................................. 1041 29.3 Register Descriptions ....................................................................................................... 1042 29.3.1 A/D Conversion Data Registers (ADDRA to ADDRD) ......................... 1043 29.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1044 29.4 ...
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LCDC Interrupt Control Register (LDINTR) ..................................................... 1085 30.3.17 LCDC Power Management Mode Register (LDPMMR).................................... 1087 30.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1089 30.3.19 LCDC Control Register (LDCNTR) ................................................................... 1090 30.4 Operation.......................................................................................................................... 1092 30.4.1 Size of LCD Modules ...
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User Break Controller Stop Function............................................................................... 1143 31.7.1 Transition to User Break Controller Stopped State............................................. 1143 31.7.2 Cancelling the User Break Controller Stopped State .......................................... 1143 31.7.3 Examples of Stopping and Restarting the User Break Controller....................... 1144 Section 32 List ...
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C. Pin Functions ................................................................................................................... 1303 C.1 Pin States............................................................................................................. 1303 C.2 Handling of Unused Pins .................................................................................... 1312 D. Synchronous DRAM Address Multiplexing Tables......................................................... 1313 E. Instruction Prefetching and Its Side Effects ..................................................................... 1324 F. Power-on and Power-off Procedures................................................................................ 1325 F.1 Power-on ...
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Rev. 2.00 Feb. 12, 2010 Page lviii of lxxxii REJ09B0554-0200 ...
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Section 1 Overview Figure 1.1 SH7760 Block Diagram .........................................................................................10 Figure 1.2 SH7760 Pin Arrangement (BP-256F/BP-256FV) ..................................................11 Figure 1.3 SH7760 Pin Arrangement (BP-256B/BP-256BV) .................................................12 Section 2 Programming Model Figure 2.1 Data Formats ..........................................................................................................39 Figure 2.2 CPU Register Configuration in Each Processing ...
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Figure 6.9 Flowchart of Memory Access Using UTLB .......................................................... 132 Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................ 133 Figure 6.11 Operation of LDTLB Instruction............................................................................ 135 Figure 6.12 Memory-Mapped ITLB Address Array.................................................................. 144 Figure 6.13 Memory-Mapped ITLB Data Array ...
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Figure 10.8 Example of 16-Bit Data Width SRAM Connection ...............................................313 Figure 10.9 Example of 8-Bit Data Width SRAM Connection .................................................313 Figure 10.10 SRAM Interface Wait Timing (Software Wait Only) ............................................314 Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by ...
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Figure 10.42 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 358 Figure 10.43 Example of 32-Bit Data Width MPX Connection.................................................. 360 Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) ........ 360 ...
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Figure 11.11 Example of DMA Transfer in Burst Mode.............................................................436 Figure 11.12 Bus Handling with Two DMAC Channels Operating ............................................440 Figure 11.13 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read ...
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Figure 11.33 Example of SSI DMA Transfer Operation Flow.................................................... 472 Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer................ 474 Figure 11.35 HAC/SSI DMA Transfer Operation Flow Using an Interrupt................................ 475 Figure 11.36 8-Bit Data Transfer for SSI ...
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Section 16 Compare Match Timer (CMT) Figure 16.1 Block Diagram of CMT .........................................................................................547 Figure 16.2 Edge Detection .......................................................................................................560 Figure 16.3 32-Bit Timer Mode: Input Capture.........................................................................560 Figure 16.4 Output Pin Assertion Period...................................................................................561 Figure 16.5 32-Bit Timer Mode: Output Compare....................................................................561 Figure 16.6 ...
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Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode ....................................... 625 Figure 17.23 Example of Synchronization Clock Transfer by DMAC ....................................... 626 Section 18 SIM Card Module (SIM) Figure 18.1 Block Diagram of SIM........................................................................................... 628 Figure 18.2 Data Format Used ...
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Figure 20.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length) ...................................................................................................................728 Figure 20.10 Inverted Clock ........................................................................................................729 Figure 20.11 Inverted Word Select.............................................................................................. 729 Figure 20.12 Inverted Padding Polarity .......................................................................................729 Figure 20.13 Padding Bits First, Followed by Serial Data, with ...
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Section 25 Audio Codec Interface (HAC) Figure 25.1 Block Diagram ....................................................................................................... 910 Figure 25.2 AC97 Frame Slot Structure .................................................................................... 926 Figure 25.3 Initialization Sequence ........................................................................................... 929 Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write .......................................... 930 Figure 25.5 Sample ...
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Figure 26.18 Example of Command Sequence for Commands with Write Data (Stream Transfer) ...................................................................................................986 Figure 26.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) ..........................................................................................987 Figure 26.20 Example of Operational Flow for Commands with Write Data ...
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Section 30 LCD Controller (LCDC) Figure 30.1 LCDC Block Diagram.......................................................................................... 1064 Figure 30.2 Valid Display and the Retrace Period .................................................................. 1092 Figure 30.3 Color-Palette Data Format.................................................................................... 1094 Figure 30.4 Power-Supply Control Sequence and States of the LCD Module ........................ 1099 ...
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Figure 33.12 PLL Synchronization Settling Time in Case of RESET, MRESET or NMI Interrupt ....................................................................................................... 1235 Figure 33.13 PLL Synchronization Settling Time in Case of IRL Interrupt.............................. 1235 Figure 33.14 MD pins Setup/Hold Timing ................................................................................ 1236 Figure 33.15 Control Signal ...
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Figure 33.38 Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) ....................... 1261 Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET) .......................... 1262 Figure 33.40 PCMCIA Memory Bus Cycle .............................................................................. 1263 Figure 33.41 PCMCIA I/O Bus Cycle....................................................................................... 1264 Figure ...
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Figure 33.78 LCDC Module Signal Timing .............................................................................. 1292 Figure 33.79 HAC Cold Reset Timing ...................................................................................... 1293 Figure 33.80 HAC Cold Reset Timing ...................................................................................... 1293 Figure 33.81 HAC Clock Input Timing..................................................................................... 1293 Figure 33.82 HAC Interface Module Signal Timing ................................................................. 1294 ...
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Rev. 2.00 Feb. 12, 2010 Page lxxiv of lxxxii REJ09B0554-0200 ...
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Section 1 Overview Table 1.1 Features ..................................................................................................................2 Table 1.2 Pin Configuration (BP-256F: 21 mm) ....................................................................13 Table 1.3 Pin Configuration (BP-256B: 17 mm)....................................................................22 Table 1.4 Pin Functions..........................................................................................................31 Table 1.5 Pin Functions..........................................................................................................32 Table 1.6 Pin Functions..........................................................................................................35 Section 2 Programming Model Table 2.1 ...
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Section 7 Caches Table 7.1 Cache Features (EMODE = 0) ............................................................................... 151 Table 7.2 Cache Features (EMODE = 1) ............................................................................... 151 Table 7.3 Store Queue Features ............................................................................................. 152 Table 7.4 Register Configuration (1)...................................................................................... 155 Table 7.4 Register Configuration (2)...................................................................................... 155 ...
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Table 10.16 Example of Correspondence between SH7760 and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0) ........................321 Table 10.17 Availability of Pipelined Access for Cycles...........................................................336 Table 10.18 Relationship between Address and CE When ...
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Table 14.3 Register Configuration (2)...................................................................................... 514 Table 14.4 Bit Assignment of CLKSTP00 and CLKSTPCLR00............................................. 517 Section 15 Timer Unit (TMU) Table 15.1 Pin Configuration ................................................................................................... 534 Table 15.2 Register Configuration (1)...................................................................................... 535 Table 15.2 Register Configuration (2)...................................................................................... 536 Table 15.3 ...
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Table 20.2 Register Configuration (1)......................................................................................709 Table 20.2 Register Configuration (2)......................................................................................709 Table 20.3 Bus Formats of SSI Module ...................................................................................722 Table 20.4 Number of Padding Bits for Each Valid Configuration .........................................726 Section 21 USB Host Module (USB) Table 21.1 Pin Configuration ...................................................................................................745 ...
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Table 26.6 Card States in which Command Sequence Is Halted ............................................. 951 Table 26.7 MMCIF Interrupt Sources...................................................................................... 990 Section 27 Multifunctional Interface (MFI) Table 27.1 Pin Configuration ................................................................................................... 999 Table 27.2 Register Configuration (1).................................................................................... 1000 Table 27.2 Register Configuration (2).................................................................................... ...
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Section 31 User Break Controller (UBC) Table 31.1 Register Configuration (1).................................................................................... 1121 Table 31.1 Register Configuration (2).................................................................................... 1122 Section 33 Electrical Characteristics Table 33.1 Absolute Maximum Ratings................................................................................. 1225 Table 33.2 DC Characteristics (T Table 33.3 Permissible Output Currents................................................................................. 1228 Table ...
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Table B.5 Clock Input........................................................................................................... 1302 Table C.1 Pin States in Reset, Power-Down State, and Bus-Released State ........................ 1303 Table G.1 SH7760 Product Lineup ....................................................................................... 1328 Table H.1 Register Configuration ......................................................................................... 1329 Rev. 2.00 Feb. 12, 2010 Page lxxxii of lxxxii ...
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SH7760 Features This LSI is a microcomputer, featuring an LCD controller, USB host, and other peripheral functions. The SuperH™ RISC engine is a Renesas Technology-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH™ RISC engine employs a fixed-length ...
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The features of this LSI are listed in table 1.1. Table 1.1 Features Item Features • LSI Operating frequency: 200 MHz • Performance: 360MIPS, 1.4 GFLOPS • Voltage: 1.5 V (internal), 3.3 V (I/O) • Superscalar architecture: Parallel execution of ...
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Item Features • FPU On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation ...
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Item Features • Clock pulse Choice of main clock times EXTAL generator (CPG) • Clock modes: ⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Bus frequency: 1, 1/2, 1/3, 1/4, ...
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Item Features • Cache memory Instruction cache (IC) ⎯ 16-Kbyte, 2-way set associative (LRU) ⎯ 256 entries, 32-byte block length ⎯ Cache-double-mode (16-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 32-Kbyte, 2-way set associative (LRU) ⎯ 512 entries, ...
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Item Features • Bus state Supports external memory access controller (BSC) • External memory space divided into seven areas, each Mbytes, with the following parameters settable for each area: ⎯ Bus size (8, 16 ...
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Item Features • Serial Three full-duplex communications channels communication • On-chip 128-byte FIFOs for all channels interface • Choice of asynchronous mode or synchronous mode (SCIF) • Can select any bit rate generated by on-chip baud-rate generator On-chip modem control ...
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Item Features • Controller area 2 channels (maximum) network 2 (HCAN2) • Supports CAN specification 2.0A and 2.0B ⎯ Standard data and remote frame (11-bit ID) ⎯ Extended data and remote frame (29-bit ID) • 32 independent message buffers using ...
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... I/O port (69 for I/O and one for output) Product lineup Group SH7760 Voltage Operating Frequency Part No. 1.5 V 200 MHz Rev. 2.00 Feb. 12, 2010 Page 9 of 1330 Package HD6417760BL200A 256-pin BGA (BP-256B) HD6417760BL200AV HD6417760BL200AD HD6417760BL200ADV HD6417760BP200AD 256-pin BGA (BP-256F) HD6417760BP200ADV REJ09B0554-0200 ...
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Block Diagram CPU I cache ITLB CPG INTC TMU H-UDI 26-bit address bus Legend: : Bus state controller BSC : Direct memory access controller DMAC : Floating-point unit FPU : User break controller UBC : Instruction translation lookaside buffer ...
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Pin Arrangement HSPI_TX/ SSI0_SCK/ SIM_D/ HAC_SD_IN0/ A EXTAL XTAL VDD-CPG VDD-PLL1 BS2 MCDAT SSI0_WS/ RESET B VSS-CPG VDD-PLL2 VSS-PLL1 HSPI_RX HAC_SYNC0 SSI1_SDATA SSI0_SDATA/ HAC_ HAC_ HAC_ RDY HAC_RES C BIT_CLK0 VSS-PLL2 SD_OUT0 SD_OUT1 SSI1_SCK/ ...
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HSPI_TX/ SSI0_SCK/ SIM_D/ HAC_SD_IN0/ BS2 A MCDAT EXTAL XTAL VDD-CPG VDD-PLL1 SSI0_WS/ RESET B HSPI_RX VSS-CPG VDD-PLL2 VSS-PLL1 HAC_SYNC0 SSI1_SDATA/ SSI0_SDATA/ HAC_ HAC_ HAC_ HAC_RES C RDY BIT_CLK0 SD_OUT0 SD_OUT1 VSS-PLL2 SSI1_SCK/ SSI1_WS/ HAC_ HAC_ ...
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... Table 1.2 lists the pin configuration of the BP-256F (21 mm* configuration of the BP-256B (17 mm* and input/output, respectively. In the GPIO column, O indicates a pin which also functions as a general I/O port. Notes: 1. HD6417760BP200AD, HD6417760BP200ADV 2. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD, HD6417760BL200ADV Table 1.2 Pin Configuration (BP-256F: 21 mm) Pin No. ...
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Pin No. Pin Name B4 VSS-PLL1 B5 SSI0_WS/HAC_SYNC0 B6 HSPI_RX HSPI_CS/SIM_RST/MCCMD B7 B8 CMT_CTR0/TCLK B9 CMT_CTR2 B10 NMI B11 SCIF1_CLK B12 SCIF1_TXD B13 SCIF1_RXD SCIF1_CTS B14 SCIF1_RTS B15 B16 SCIF0_RXD B17 MD3/CE2A B18 VSS-PLL3 B19 USB_DM B20 VDDQ RDY C1 ...
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Pin No. Pin Name C16 MD2 C17 DRAK0 C18 USB_PENC C19 VSSQ C20 USB_DP D1 DCK D2 SSI1_SCK/HAC_SD_IN1 D3 SSI1_WS/HAC_SYNC1 D4 HAC_BIT_CLK1 MRESET D5 D6 STATUS0 D7 VSS D8 STATUS1 D9 VSSQ TRST D10 D11 VSSQ D12 TDI D13 VSSQ ...
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Pin No. Pin Name DREQ1 E20 F1 MFI-D8/LCD_DATA8 F2 MFI-D0/LCD_DATA0 CS0 F3 BACK F4 F17 I2C1_SCL F18 I2C1_SDA F19 I2C0_SCL F20 I2C0_SDA G1 MFI-D9/LCD_DATA9 G2 MFI-D1/LCD_DATA1 G3 VDD G4 VSS G17 VSS G18 VDD G19 MD6/IOIS16 G20 MD5 H1 MFI-D10/LCD_DATA10 ...
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Pin No. Pin Name J20 Reserved/AUDATA[3] K1 MFI-D12/LCD_DATA12 K2 MFI-D4/LCD_DATA4/DREQ2 K3 VDDQ K4 VSSQ K17 AVss_ADC K18 AVcc_ADC ADTRG/AUDATA[0] K19 K20 Reserved/AUDATA[1] L1 MFI-D13/LCD_DATA13 L2 MFI-D5/LCD_DATA5/DRAK2/DACK2 CS4 L3 L4 A20 L17 AN3 L18 AN2 L19 AN1 L20 AN0 M1 MFI-D14/LCD_DATA14 ...
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Pin No. Pin Name IRL0 N20 MFI-INT/LCD_CLK P1 MFI-CS/LCD_DON P2 P3 VDD P4 VSS P17 VSS P18 VDD P19 CAN0_NERR/AUDCK P20 CAN1_NERR/AUDSYNC R1 MFI-E/LCD_CL1 R2 MFI-MD/LCD_CL2 CS6 R17 A24 R18 A25 R19 CAN0_RX/AUDATA[2] R20 CAN1_RX/AUDATA[3] T1 MFI-RS/LCD_M_DISP ...
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Pin No. Pin Name U8 VSSQ U9 A17 U10 VSSQ U11 VSSQ U12 VSSQ U13 A18 U14 VSS U15 A19 U16 VSSQ U17 D20 U18 D28 U19 D16 U20 D31 D14 V3 VDDQ V4 D10 V5 VDDQ ...
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Pin No. Pin Name VSSQ RD/WR WE0/DQM0/REG W10 A8 W11 A10 W12 A12 W13 A14 WE2/DQM2/ICIORD W14 RAS W15 W16 D24 W17 D25 W18 D27 ...
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Pin No. Pin Name WE3/DQM3/ICIOWR Y14 CS3 Y15 Y16 D23 Y17 D22 Y18 D26 Y19 D19 Y20 D18 In the I/O column IO, and ⎯ indicate input, output, input/output, and no direction, Legend: respectively. Notes: 1. Can be ...
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Table 1.3 Pin Configuration (BP-256B: 17 mm) Pin No. Pin Name A1 EXTAL A2 XTAL A3 VDD-CPG A4 VDD-PLL1 A5 SSI0_SCK/HAC_SD_IN0/BS2 A6 HSPI_TX/SIM_D/MCDAT A7 HSPI_CLK/SIM_CLK/MCCLK A8 CMT_CTR1 A9 CMT_CTR3 A10 SCIF2_CLK A11 SCIF2_TXD A12 SCIF2_RXD SCIF2_CTS A13 SCIF2_RTS A14 A15 ...
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Pin No. Pin Name B12 SCIF1_TXD B13 SCIF1_RXD SCIF1_CTS B14 SCIF1_RTS B15 B16 SCIF0_RXD B17 MD3/CE2A B18 VSS-PLL3 B19 USB_DM B20 VDDQ RDY C1 C2 HAC_BIT_CLK0 C3 VSS-PLL2 HAC_RES C4 C5 SSI0_SDATA/HAC_SD_OUT0 C6 SSI1_SDATA/HAC-SD_OUT1 C7 VDD ASEBRK/BRKACK C8 C9 VDDQ ...
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Pin No. Pin Name MRESET D5 D6 STATUS0 D7 VSS D8 STATUS1 D9 VSSQ TRST D10 D11 VSSQ D12 TDI D13 VSSQ D14 VSS D15 VSSQ D16 MD0 D17 MD1 D18 DRAK1 D19 DACK1 USB_OVC D20 E1 MFI-D8/LCD_DATA8 E2 VEPWC/IRQ5 ...
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Pin No. Pin Name G1 MFI-D10/LCD_DATA10 G2 MFI-D1/LCD_DATA1 G3 VDD G4 VSS G17 VSS G18 VDD G19 MD6/IOIS16 G20 MD5 CS1 H1 H2 MFI-D2/LCD_DATA2/IRQ6 H3 VDDQ H4 VSSQ H17 MD7 H18 MD8 H19 Reserved/AUDCK H20 Reserved/AUDSYNC J1 MFI-D11/LCD_DATA11 J2 MFI-D3/LCD_DATA3/IRQ7 ...
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Pin No. Pin Name L1 MFI-D13/LCD_DATA13 L2 MFI-D6/LCD_DATA6/DREQ3 L3 MFI-D5/LCD_DATA5/DRAK2/DACK2 L4 A20 L17 AN3 L18 AN2 L19 AN1 L20 AN0 M1 MFI-D14/LCD_DATA14 M2 MFI-D7/LCD_DATA7/DRAK3/DACK3 M3 A21 M4 VDDQ M17 VSSQ M18 VDDQ IRL3 M19 IRL2 M20 CS5 N1 MFI-INT/LCD_CLK N2 ...
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Pin No. Pin Name MFI-E/LCD_CL1 R4 A0 R17 A24 R18 A25 R19 CAN0_RX/AUDATA[2] R20 CAN1_RX/AUDATA[3] T1 MFI-RW/LCD_FLM T2 MFI-RS/LCD_M_DISP T3 D11 T4 MFI-MD/LCD_CL2 T17 A22 T18 A23 T19 CAN0_TX/AUDATA[0] T20 CAN1_TX/AUDATA[1] U1 D15 U2 D0 ...
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Pin No. Pin Name U17 D20 U18 D28 U19 D16 U20 D31 V1 D14 VDDQ V4 D10 V5 VDDQ VDD V8 VDDQ V9 A7 V10 VDDQ V11 VDDQ V12 VDDQ V13 A15 V14 VDD ...
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Pin No. Pin Name W10 A8 W11 A10 W12 A12 W13 A14 WE2/DQM2/ICIORD W14 RAS W15 W16 D24 W17 D25 W18 D27 W19 VSSQ W20 D29 Y1 D13 Y2 D12 RD/CASS/FRAME Y6 WE1/DQM1 Y7 ...
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In the I/O column IO, and ⎯ indicate input, output, input/output, and no direction, Legend: respectively. Notes: 1. Can be used as a GPIO interrupt pin. 2. Can be used as a GPIO interrupt pin. When an interrupt ...
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Pin Function Table 1.4 Pin Functions Rev. 2.00 Feb. 12, 2010 Page 31 of 1330 REJ09B0554-0200 ...
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Table 1.5 Pin Functions Rev. 2.00 Feb. 12, 2010 Page 32 of 1330 REJ09B0554-0200 ...
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Rev. 2.00 Feb. 12, 2010 Page 33 of 1330 REJ09B0554-0200 ...
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Rev. 2.00 Feb. 12, 2010 Page 34 of 1330 REJ09B0554-0200 ...
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Table 1.6 Pin Functions Pin No mm* 21 mm* Function R4 R4 Address W10 W10 Y11 Y11 W11 W11 Y12 Y12 W12 W12 ...
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Pin No mm* 21 mm* Function Y3 Y3 Data U19 U19 V19 V19 Y20 Y20 Y19 Y19 ...
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Pin No mm* 21 mm* Function Y15 Y15 Chip select Read/Write RAS W15 W15 Y6 Y6 Read/CAS/FRAME W7 W7 Selection signal for D7 to D0/REG Y7 Y7 Selection signal ...
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... E3 E3 Chip active D6 D6 Status Status External input clock/crystal resonator A2 A2 Crystal resonator Notes: 1. HD6417760BL200A, HD6417760BL200AV, HD6417760BL200AD, HD6417760BL200ADV 2. HD6417760BP200AD, HD6417760BP200ADV Rev. 2.00 Feb. 12, 2010 Page 38 of 1330 REJ09B0554-0200 Memory Interface Pin Name I/O SRAM SDRAM PCMCIA CA I STATUS0 O STATUS1 O EXTAL I XTAL ...
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Section 2 Programming Model 2.1 Data Formats The data formats supported in the SH-4 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits) Double-precision floating-point (64 bits ...
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Register Descriptions 2.2.1 Privileged Mode and Banks Processor Modes: This LSI has two processor modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt ...
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Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or ...
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R0 _ BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 R10 R11 R12 ...
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General Registers Figure 2.3 shows the relationship between the processing modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed ...
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Control Registers The control registers are 32 bits long. They consist of the status register (SR), global base register (GBR), saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug ...
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Bit Bit Name Initial Value R — All — All — — 7 IMASK3 1 6 IMASK2 1 5 IMASK1 1 4 IMASK0 1 3, ...
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Saved General Register 15 (SGR): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug Base Register (DBR): When the user break debugging function is enabled (BRCR.UBDE = 1), DBR is referenced as ...
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H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do ...
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Address A Byte 0 15 Address Word 0 31 Address Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) ...
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Power-Down State power-down state, CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are three modes in the power-down state: sleep mode, deep sleep mode, and standby mode. ...
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Processing Modes There are two processing modes: user mode and privileged mode. The processing mode is determined by the processing mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to ...
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Section 3 Floating-Point Unit (FPU) 3.1 Features The FPU has the following features. • Designed to meet IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and ...
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The exponent is expressed in biased form, as follows bias The range of unbiased exponent distinguished as follows. E min denormalized number, and E Table 3.1 shows E and E min max Table ...
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Table 3.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number 3.2.2 Non-Numbers (NaN) Figure 3.3 shows the ...
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N = 1:sNaN N = 0:qNaN Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. • When the EN.V bit in FPSCR ...
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Register Descriptions 3.3.1 Floating-Point Registers Figure 3.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) ...
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FPSCR. FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FR10 FR11 FV12 DR12 FR12 FR13 DR14 FR14 FR15 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 Rev. 2.00 Feb. 12, ...
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Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Do not set the SZ and PR bits to 1 simultaneously; this setting is reserved. Bit ...
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Bit Bit Name Initial Value Cause All Enable All Flag All 0 1 RM1 0 0 RM0 1 Table 3.3 Bit Allocation for FPU Exception Handling Field Name Cause ...
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Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic ...
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The FPU exception cause field in FPSCR contains bits corresponding to all of above sources and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources ...
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Underflow (U): When FPSCR. denormalized number with the same sign as the unrounded value, or zero with the same sign as the unrounded value, is generated. When FPSCR. zero with the same sign as ...
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This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 × 4 matrix, the FPU supports 4-dimensional operations. • Matrix (4 ...
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SZ bit in FPSCR cleared to 0. 3.7 Usage Notes 3.7.1 Rounding Mode and Underflow Flag When using the Round to Nearest rounding mode, the underflow ...
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Operation result: H'00100000 00000000 FPSCR: H'000C300C b. FPU Operation result: H'00100000 00000000 FPSCR: H'000C1004 Workarounds 1. Use FPSCR.RM = 01, that is to say Round to Zero rather than Round to Nearest mode. 2. Use FPSCR.RM = 00, that is ...
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Sign of Operation Result when Using FIPR or FTRV Instruction When two or more data items used in an operation by the FIPR or FTRV instruction are infinity, and all of the infinity items in the multiplication results have ...
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Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001, the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and FPSCR.Cause.I should ...
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Execution Environment PC: At the start of instruction execution, the PC indicates the address of the instruction itself. • Data sizes and data types The SH-4 instruction set is implemented with 16-bit fixed-length instructions. The SH-4 can use byte ...
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ADD # bit is not changed by ADD operation CMP/EQ R1 R1, T bit is set TARGET ; Branches to TARGET if T bit = 1 (R0 = R1) ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 4.1. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If ...
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Addressing Instruction Mode Format Register @(disp:4, Rn) indirect with displacement Indexed @(R0, Rn) register indirect GBR indirect @(disp:8, GBR) Effective address is register GBR contents with with displacement Indexed @(R0, GBR) GBR indirect Rev. 2.00 Feb. 12, 2010 Page 70 ...
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Addressing Instruction Mode Format PC-relative @(disp:8, PC) Effective address with 8-bit displacement with displacement PC-relative disp:8 Effective Address Calculation Method disp added. After disp is zero-extended multiplied by 2 (word (longword), according ...
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Addressing Instruction Mode Format PC-relative disp:12 Rn Immediate #imm:8 #imm:8 #imm:8 Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed according ...
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Instruction Set Table 4.2 shows the notation used in the SH instruction lists shown in tables 4.3 to 4.12. Table 4.2 Notation Used in Instruction List Item Format Instruction OP.Sz SRC, DEST mnemonic Summary of operation MSB ↔ LSB ...
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Table 4.3 Fixed-Point Transfer Instructions Instruction Operation imm → sign extension → Rn MOV #imm,Rn (disp × → sign MOV.W @(disp,PC),Rn extension → Rn (disp × & H'FFFF FFFC MOV.L @(disp,PC),Rn + ...
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Instruction Operation R0 → (disp + GBR) MOV.B R0,@(disp,GBR) R0 → (disp × GBR) MOV.W R0,@(disp,GBR) R0 → (disp × GBR) MOV.L R0,@(disp,GBR) (disp + GBR) → MOV.B @(disp,GBR),R0 sign extension → R0 (disp × 2 ...
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Instruction Operation When Rn > → T CMP/PL Rn Otherwise, 0 → T CMP/STR Rm,Rn When any bytes are equal, 1 → T Otherwise, 0 → T 1-step division (Rn ÷ Rm) DIV1 Rm,Rn MSB of Rn → ...
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Instruction Operation Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — SUBC Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — SUBV Rm,Rn Table 4.5 Logic Operation Instructions Instruction Operation Rn & Rm → Rn ...
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Table 4.6 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL Rn LSB → Rn → T ROTR Rn T ← Rn ← T ROTCL Rn T → Rn → T ROTCR Rn When Rm ≥ << ...
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Table 4.7 Branch Instructions Instruction Operation When disp × label 4 → PC When nop BF/S label Delayed branch; when disp × ...
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Table 4.8 System Control Instructions Instruction CLRMAC CLRS CLRT LDC Rm,SR LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR LDC Rm,SPC LDC Rm,DBR LDC Rm,Rn_BANK LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+,DBR LDC.L @Rm+,Rn_BANK LDS Rm,MACH LDS ...
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Instruction SETS SETT SLEEP STC SR,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn STC SPC,Rn STC SGR,Rn STC DBR,Rn STC Rm_BANK,Rn STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L SGR,@-Rn STC.L DBR,@-Rn STC.L Rm_BANK,@-Rn STS MACH,Rn STS MACL,Rn ...
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Table 4.9 Floating-Point Single-Precision Instructions Instruction Operation H'0000 0000 → FRn FLDI0 FRn H'3F80 0000 → FRn FLDI1 FRn FRm → FRn FMOV FRm,FRn (Rm) → FRn FMOV.S @Rm,FRn (R0 + Rm) → FRn FMOV.S @(R0,Rm),FRn (Rm) → FRn, Rm ...
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Table 4.10 Floating-Point Double-Precision Instructions Instruction Operation FABS DRn DRn & H'7FFF FFFF FFFF FFFF → DRn DRn + DRm → DRn FADD DRm,DRn When DRn = DRm, 1 → T FCMP/EQ DRm,DRn Otherwise, 0 → T When DRn > ...
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Table 4.12 Floating-Point Graphics Acceleration Instructions Instruction Operation DRm → XDn FMOV DRm,XDn XDm → DRn FMOV XDm,DRn XDm → XDn FMOV XDm,XDn (Rm) → XDn FMOV @Rm,XDn (Rm) → XDn → Rm FMOV @Rm+,XDn (R0 + ...
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The four words of data following the TRAPA instruction or undefined instruction code H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access (read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the ...
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Workarounds: To prevent the problem, use either of workarounds below. a. Include a NOP instruction in the eight words of data following each TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD. b. Include an OR R0,R0 ...
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The SH 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. The definitions in this section may not be applied ...
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General Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read ...
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EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS ...
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OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 ...
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LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC. from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles ...
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STS.L from MACH/L: 1 issue cycle D I 32. LDS to FPSCR: 1 issue cycle D I 33. LDS.L to FPSCR: 1 issue cycle D I 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU ...
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Double-precision FCMP: 2 issue cycles FCMP/EQ, FCMP/ 41. Double-precision FDIV/FSQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle ...
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Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 5.1. Table 5.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group ...
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LS Group FABS DRn FABS FRn FLDI0 FRn FLDI1 FRn FLDS FRm,FPUL FMOV @(R0,Rm),DRn FMOV @(R0,Rm),XDn FMOV @Rm,DRn FMOV @Rm,XDn FMOV @Rm+,DRn FMOV @Rm+,XDn FMOV DRm,@(R0,Rn) FMOV DRm,@-Rn FMOV DRm,@Rn FMOV DRm,DRn FMOV DRm,XDn FMOV FRm,FRn FMOV XDm,@(R0,Rn) FMOV ...
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CO Group AND.B #imm,@(R0,GBR) LDS BRAF Rm BSRF Rm CLRMAC CLRS DMULS.L Rm,Rn DMULU.L Rm,Rn FCMP/EQ DRm,DRn FCMP/GT DRm,DRn JMP @Rn JSR @Rn LDC Rm,DBR LDC Rm,GBR LDC Rm,Rp_BANK LDC Rm,SPC LDC Rm,SR LDC Rm,SSR LDC Rm,VBR LDC.L @Rm+,DBR ...
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Table 5.2 Parallel-Executability 1st MT Instruction Legend: O: Can be executed in parallel X: Cannot be executed in parallel 5.3 Execution Cycles and Pipeline Stalling This LSI has three basic clocks: CPU clock (Ick), bus ...
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The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 5.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back ...
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For example, when FADD follows FDIV with no dependency between floating-point registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, ...
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Serial execution: Non-parallel-executable instructions SHAD R0,R1 I ADD R2,R3 I next (b) Parallel execution: Parallel-executable and no dependency ADD R2,R1 I MOV.L @R4,R5 I (c) Issue rate: Multi-step instruction AND.B#1,@(R0,GBR) I MOV R1,R2 I next 4 stall cycles (d) ...
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Flow dependency I D MOV R0,R1 ADD R2, ADD R2, MOV.L @R1,R1 next I 1 stall cycle I D MOV.L @R1,R1 ADD R0,R1 I next MOV.L @R1,R1 I SHAD R1,R2 ...
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Flow dependency (cont) I LDS R0,FPUL FLOAT FPUL,FR0 LDS R1,FPUL FLOAT FPUL,R1 I FTRC FR0,FPUL STS FPUL,R0 FTRC FR1,FPUL STS FPUL,R1 (f) Output dependency I FSQRT FR4 FMOV FR0,FR4 I FADD DR0,DR2 I I FMOV FR0,FR3 (g) Anti-flow dependency ...
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Resource conflict FDIV FR6,FR7 FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 I D FIPR FV8,FV0 I FADD FR15,FR4 LDS.L @R15+, STC GBR, FADD DR0,DR2 I MAC.W @R1+,@R2+ MAC.W @R1+,@R2 ...
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Table 5.3 Execution Cycles Functional Category No. Instruction Data transfer 1 EXTS.B Rm,Rn instructions 2 EXTS.W Rm,Rn 3 EXTU.B Rm,Rn 4 EXTU.W Rm,Rn 5 MOV Rm,Rn 6 MOV #imm,Rn 7 MOVA @(disp,PC),R0 8 MOV.W @(disp,PC),Rn 9 MOV.L @(disp,PC),Rn 10 MOV.B ...
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Functional Category No. Instruction Data transfer 34 MOV.B Rm,@(R0,Rn) instructions 35 MOV.W Rm,@(R0,Rn) 36 MOV.L Rm,@(R0,Rn) 37 MOV.B R0,@(disp,GBR) 38 MOV.W R0,@(disp,GBR) 39 MOV.L R0,@(disp,GBR) 40 MOVCA.L R0,@Rn 41 MOVT Rn 42 OCBI @Rn 43 OCBP @Rn 44 OCBWB @Rn ...
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Functional Category No. Instruction Fixed-point 68 MAC.L @Rm+,@Rn+ arithmetic 69 MAC.W @Rm+,@Rn+ instructions 70 MUL.L Rm,Rn 71 MULS.W Rm,Rn 72 MULU.W Rm,Rn 73 NEG Rm,Rn 74 NEGC Rm,Rn 75 SUB Rm,Rn 76 SUBC Rm,Rn 77 SUBV Rm,Rn Logical 78 AND ...
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Functional Category No. Instruction Shift 102 SHLL8 Rn instructions 103 SHLL16 Rn 104 SHLR Rn 105 SHLR2 Rn 106 SHLR8 Rn 107 SHLR16 Rn Branch 108 BF disp instructions 109 BF/S disp 110 BT disp 111 BT/S disp 112 BRA ...
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Functional Category No. Instruction System 136 LDC.L @Rm+,DBR control 137 LDC.L @Rm+,GBR instructions 138 LDC.L @Rm+,Rp_BANK CO 139 LDC.L @Rm+,SR 140 LDC.L @Rm+,SSR 141 LDC.L @Rm+,SPC 142 LDC.L @Rm+,VBR 143 LDS Rm,MACH 144 LDS Rm,MACL 145 LDS Rm,PR 146 LDS.L ...
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Functional Category No. Instruction Single- 171 FLDI0 FRn precision 172 FLDI1 FRn floating-point 173 FMOV FRm,FRn instructions 174 FMOV.S @Rm,FRn 175 FMOV.S @Rm+,FRn 176 FMOV.S @(R0,Rm),FRn 177 FMOV.S FRm,@Rn 178 FMOV.S FRm,@-Rn 179 FMOV.S FRm,@(R0,Rn) 180 FLDS FRm,FPUL 181 FSTS ...
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Functional Category No. Instruction Double- 201 FABS DRn precision 202 FADD DRm,DRn floating-point instructions 203 FCMP/EQ DRm,DRn 204 FCMP/GT DRm,DRn 205 FCNVDS DRm,FPUL 206 FCNVSD FPUL,DRn 207 FDIV DRm,DRn 208 FLOAT FPUL,DRn 209 FMUL DRm,DRn 210 FNEG DRn 211 FSQRT ...
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Functional Category No. Instruction Graphics 231 FIPR FVm,FVn acceleration 232 FRCHG instructions 233 FSCHG 234 FTRV XMTRX,FVn Notes: 1. See table 5.1 for the instruction groups. 2. Latency "L1/L2... ": Latency corresponding to a write to each register, including MACH/MACL/FPSCR. ...
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In the case of consecutive executions of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/ DMULS.L/DMULU.L, latency is decreased to 2 cycles. 6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn instruction, latency of the LDS to MACH/MACL is 4 cycles. 7. ...
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Section 6 Memory Management Unit (MMU) The SH-4 supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit external memory space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit ...
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When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. ...
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Physical Memory Process 1 6.1.1 Address Spaces (1) Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the AT bit in MMUCR is cleared to 0 and the MMU is ...
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H'0000 0000 Cacheable H'8000 0000 Cacheable H'A000 0000 Non-cacheable H'C000 0000 Cacheable H'E000 0000 Non-cacheable H'FFFF FFFF Privileged mode Figure 6.2 Physical Address Space ( MMUCR) Access to a PCMCIA interface area by the CPU in SH7760 ...