HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet
HD6417751RF240V
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HD6417751RF240V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7751 Group, 32 SH7751R Group Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.4.00 Oct. 10, 2008 Page iv of xcviii REJ09B0370-0400 ...
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The SH-4 (SH7751 Group (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Group is built in with a variety of peripheral functions such as cache ...
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User manuals for SH7751 and SH7751R Name of Document SH7751 Group, SH7751R Group Hardware Manual SH-4 Software Manual • User manuals for development tools Name of Document SuperH™ C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH™ RISC engine ...
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Main Revisions for This Edition Item Page ⎯ All 1.1 SH7751/SH7751R 1 Group Features Table 1.1 2 SH7751/SH7751R Group Features Revision (See Manual for Details) Notification of change in company name amended Hitachi, Ltd. → Renesas Technology Corp. Description amended ...
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Item Page 1.1 3 SH7751/SH7751R Group Features Table 1.1 SH7751/SH7751R Group Features 8 Rev.4.00 Oct. 10, 2008 Page viii of xcviii REJ09B0370-0400 Revision (See Manual for Details) Table amended Item Features • Floating-point registers: 32 bits × 16 × 2 ...
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Item Page 1.2 Block Diagram 9 Figure 1.1 Block Diagram of SH7751 Series Functions Revision (See Manual for Details) Figure amended CPU UBC Lower 32-bit data Cache and I cache ITLB UTLB TLB controller CPG INTC BSC SCI (SCIF) RTC ...
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Item Page 1.3 Pin Arrangement 12 Figure 1.4 Pin Arrangement (292-Pin BGA) 1.4.1 Pin Functions 14 (256-Pin QFP) Table 1.2 Pin Functions 20 23 Rev.4.00 Oct. 10, 2008 Page x of xcviii REJ09B0370-0400 Revision (See Manual for Details) Newly added ...
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Item Page 1.4.2 Pin Functions 25 (256-Pin BGA) Table 1.3 Pin Functions 34 1.4.3 Pin Functions Newly added (292-Pin BGA) 2.2.1 Privileged Mode 49 and Banks Table 2.1 Initial Register Values 2.6 Processor States 61 Figure 2.6 ...
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Item Page 3.3.7 Address Space 77, 78 Identifier (ASID) 3.5.5 Avoiding 87 Synonym Problems 3.8 Usage Notes 100 4.1.1 Features 101 Rev.4.00 Oct. 10, 2008 Page xii of xcviii REJ09B0370-0400 Revision (See Manual for Details) Note amended Notes: 2. When ...
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Item Page 4.2 Register 104 Descriptions • ORA: OC RAM 3 enable bit* 4.3.1 Configuration 108 LRU (SH7751R only) 4.3.10 Notes on Using 114 to OC RAM Mode 116 (SH7751R Only) when in Cache Enhanced Mode 4.4.1 Configuration 119 LRU ...
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Item Page 5.3.2 Exception 139 Handling Vector Addresses 5.4 Exception Types 142 and Priorities Table 5.2 Exceptions 5.5.3 Exception 146 Requests and BL Bit 5.6.1 Resets 147 (1) Power-On Reset (2) Manual Reset 148 Rev.4.00 Oct. 10, 2008 Page xiv ...
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Item Page 5.6.1 Resets 149 (3) H-UDI Reset (4) Instruction TLB 150 Multiple-Hit Exception (5) Data TLB Multiple- 151 Hit Exception 5.6.2 General 162 Exceptions (11) General FPU Disable Exception Revision (See Manual for Details) Description amended In the initialization ...
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Item Page 5.7 Usage Notes 170 6.5 Floating-Point 182 Exceptions 6.6.2 Pair Single- 184 Precision Data Transfer 6.7 Usage Notes 185 to 188 7.3 Instruction Set 207 Table 7.12 Floating- Point Graphics Acceleration Instructions 7.4 Usage Notes 207 to 209 ...
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Item Page 9.1.1 Types of Power- 239 Down Modes 9.2.4 Standby Control 245 Register 2 (STBCR2) 9.6.2 Exit from Standby 251 Mode 9.8.1 Transition to 253 Hardware Standby Mode 9.8.2 Exit from 253, 254 Description replaced Hardware Standby Mode 9.8.3 ...
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Item Page 9.9.1 In Reset 255 Figure 9.2 STATUS Output in Manual Reset 9.9.5 Hardware 264 Standby Mode Timing Figure 9.15 Timing When VDD-RTC Power is Off → On 9.10 Usage Notes 264, 265 Newly added 10.1.1 Features 267 Rev.4.00 ...
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Item Page 10.2.1 Block Diagram 271 of CPG PLL Circuit 1: 10.3 Clock Operating 273 Modes Table 10.3 (1) Clock Operating Modes (SH7751) 10.3 Clock Operating 274 Modes Table 10.4 FRQCR Settings and Internal Clock Frequencies Revision (See Manual for ...
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Item Page 10.10 Notes on Board 288 Design Figure 10.5 Points for Attention when Using PLL Oscillator Circuit 10.11 Usage Notes 289 11.1.2 Block Diagram 292 Figure 11.1 Block Diagram of RTC 11.1.3 Pin 293 Configuration Table 11.1 RTC Pins ...
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Item Page 12.2.7 Input Capture 326 Register 2 (TCPR2) 12.4 Interrupts 332 12.5.4 External Clock 333 Frequency 13.1.4 Register 340 Configuration Table 13.2 BSC Registers 13.1.6 PCMCIA 347 Support Table 13.5 PCMCIA Support Interfaces 13.2.3 Bus Control 359 Register 3 ...
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Item Page 13.2.8 Memory Control 377 Register (MCR) 13.2.8 Memory Control 378 Register (MCR) 379 380 13.2.10 Synchronous 387 DRAM Mode Register (SDMR) Rev.4.00 Oct. 10, 2008 Page xxii of xcviii REJ09B0370-0400 Revision (See Manual for Details) Description amended of ...
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Item Page 13.3.2 Areas 400 Area 0: Area 1: Area 2: 401 Area 3: Area 4: 402 Area 5: 403 Area 6: 404 13.3.3 SRAM Interface 412 Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) Revision ...
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Item Page 13.3.3 SRAM Interface 412 Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) 13.3.4 DRAM Interface 425 Refresh: • Self-Refresh • Relationship between 426 Refresh Requests and Bus Cycle Requests Figure 13.22 DRAM Self-Refresh Cycle ...
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Item Page 13.3.5 Synchronous 427, 428 Description deleted DRAM Interface Figure 13.23 Example 428 of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Burst Read: 431 Figure 13.24 Basic Timing for Synchronous DRAM Burst Read Refreshing: 448 • Auto-Refreshing Figure ...
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Item Page 13.3.5 Synchronous 453 DRAM Interface Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) Changing the Burst 455 Length (SH7751R Only): • Burst Read Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst ...
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Item Page 13.3.7 PCMCIA 469 Interface Figure 13.49 Wait Timing for PCMCIA I/O Card Interface 13.3.8 MPX Interface 471 Figure 13.51 Example 472 of 32-Bit Data Width MPX Connection Revision (See Manual for Details) Figure amended ICIOWR (write) D15–D0 (write) ...
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Item Page ⎯ 13.3.8 MPX Interface Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Figure 13.65 MPX Interface Timing 6(Burst Read Cycle, AnW = ...
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Item Page 13.3.11 Bus Arbitration 490, 491 Description amended Revision (See Manual for Details) There are two bus arbitration modes: slave mode. In master mode the bus is held on a constant basis, and is released to another device in ...
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Item Page 13.3.15 Notes on 495, 496 Description amended Usage Rev.4.00 Oct. 10, 2008 Page xxx of xcviii REJ09B0370-0400 Revision (See Manual for Details) Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware standby mode, ...
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Item Page 14.1.1 Features 498, 499 Description amended 14.2.4 DMA Channel 508 Control Registers 0-3 (CHCR0-CHCR3) 14.3.4 Types of DMA 533 Transfer (a) Normal DMA Mode Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode (b) DDT ...
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Item Page 14.5.2 Pins in DDT 555 Mode Figure 14.24 shows the system configuration in DDT mode. • TR: Data Transfer Request 556 Format (DTR) Figure 14.25 Data Transfer Request Format Data Transfer Request Format (DTR) 557 14.5.4 Notes on ...
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Item Page 14.7.4 DMA Channel 591 Control Registers 0- 7(CHCR0-CHCR7) Bit 17-Acknowledge Mode (AM) 14.8.3 Transfer 596 Channel Notification in DDT Mode Table 14.17 Function of BAVL 15.1 Overview 603 15.3.3 Multiprocessor 644 Communication Function Revision (See Manual for Details) ...
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Item Page 15.3.3 Multiprocessor 649, 650 Description amended Communication Function Figure 15.15 Sample 651 Flowchart of Multiprocessor Serial Reception with Interrupt Generation Rev.4.00 Oct. 10, 2008 Page xxxiv of xcviii REJ09B0370-0400 Revision (See Manual for Details) Multiprocessor Serial Data Reception ...
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Item Page 15.3.3 Multiprocessor 652 Communication Function Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 15.5 Usage Notes 667, 668 Description added Handling of TEND Flag and TE Bit 17.1 Overview 719 ...
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Item Page 19.1.3 Pin 771 Configuration Table 19.1 INTC Pins 19.2.1 NMI Interrupt 772 19.2.2 IRL Interrupts 774 19.2.3 On-Chip 775 Peripheral Module Interrupts 19.2.4 Interrupt 777 Exception Handling and Priority Table 19.4 Interrupt Exception Handling Sources and Priority Order ...
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Item Page 19.4.1 Interrupt 788 Operation Sequence Figure 19.3 Interrupt Operation Flowchart 19.6 Usage Notes 791 to 793 20.2.1 Access to UBC 798 Registers 20.3.1 Explanation of 808 Terms Relating to Accesses 21.1.1 Features 823 Revision (See Manual for Details) ...
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Item Page 21.1.3 Pin 826 Configuration 21.2.5 Boundary Scan 829 to Register (SDBSR) 842 Table 21.3 Structure of Boundary Scan Register 21.3.4 Boundary Scan 845 (EXTEST, SAMPLE/PRELOAD, BYPASS) 21.4 Usage Notes 22.1.1 Features 847 22.1.3 Pin 850 Configuration Table 22.1 ...
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Item Page 22.2.3 PCI 864 Configuration Register 2 (PCICONF2) 22.2.17 PCI Control 886 Register (PCICR) 887 22.2.24 PCI Arbiter 900 Interrupt Register (PCIAINT) 901 Revision (See Manual for Details) Description amended Bits 23 to 16—Sub Class Codes (CLASS15 to 8): ...
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Item Page 22.2.24 PCI Arbiter 901 Interrupt Register (PCIAINT) 22.2.25 PCI Arbiter 902 Interrupt Mask Register (PCIAINTM) 22.2.29 PCI DMA 907, 908 Description amended Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) 22.2.30 PCI DMA 909 Transfer Counter Register ...
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Item Page 22.2.38 PCIC-BSC 921 Registers 922 22.2.41 PIO Data 928 Register (PCIPDR) 22.3.3 PCIC 930 Initialization Revision (See Manual for Details) Description added The PCIC-BSC performs the same type of control as the slave function of the bus controller ...
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Item Page 22.3.7 PIO Transfers 936 Figure 22.2 PIO Memory Space Access Figure 22.3 PIO I/O 937 Space Access 22.3.8 Target 939 Transfers I/O-Read and I/O-Write 940 Commands: Configuration-Read and Configuration-Write Commands: 22.3.9 DMA Transfers 945 DMA Arbitration Rev.4.00 Oct. ...
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Item Page 22.3.11 PCI Bus Basic 947 Interface Target Read/Write Cycle 952 Timing: 22.4.4 Endian Control 963 in Target Transfers (Memory Read/Memory Write) 22.6.1 Interrupts from 970 PCIC to CPU Power Management Interrupt (Transition Request to Normal Status) (PCIPWON): Power ...
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Item Page 22.9.1 Power 973 Management Overview 22.9.2 Stopping the 974, 975 Table amended Clock Table 22.14 Method of Stopping Clock per Operating Mode 22.12 Usage Notes 977 to 980 Rev.4.00 Oct. 10, 2008 Page xliv of xcviii REJ09B0370-0400 Revision ...
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Item Page Section 23 Electrical 981 to Characteristics 1080 23.1 Absolute 981 Maximum Ratings Table 23.1 Absolute Maximum Ratings 23.2 DC 982 Characteristics Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V)) Table 23.3 DC 984, 985 Table amended Characteristics (HD6417751RF240 ...
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Item Page 23.2 DC 988, 989 Table amended Characteristics Table 23.5 DC Characteristics (HD6417751RF200 (V)) ⎯ Table 23.7 DC Characteristics (HD6417751BP167I (V)) Table 23.9 DC Characteristics (HD6417751F167I (V)) Table 23.10 DC Characteristics (HD6417751VF133) 23.3 AC 994 Characteristics Table 23.9 Clock ...
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Item Page 23.3.1 Clock and 996 Control Signal Timing Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V)) Table 23.15 Clock and 997 Control Signal Timing (HD6417751RF240 (V)) Table 23.16 Clock and 998 Control Signal Timing (HD6417751RBP200 (V), ...
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Item Page 23.3.2 Control Signal 1007 Timing Table 23.20 Control Signal Timing Figure 23.12 (1) Pin 1008 Drive Timing for Rest or Sleep Mode Figure 23.12 (2) Pin 1009 Drive Timing for Software Standby Mode 23.3.3 Bus Timing 1010, 1011 ...
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Item Page 23.3.3 Bus Timing 1024 Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3) Figure 23.24 1025 Synchronous DRAM Normal Read Bus Cycle: PRE ...
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Item Page 23.3.3 Bus Timing 1036 Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) Figure 23.36 DRAM 1038 Bus Cycle (EDO Mode, RCD [1:0]=00, AnW[2:0]=000, TRC[2:0]=001) Rev.4.00 Oct. 10, 2008 Page l of xcviii REJ09B0370-0400 Revision (See ...
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Item Page 23.3.3 Bus Timing 1052 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait 23.3.4 ...
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Item Page 23.3.4 Peripheral 1069 Module Signal Timing Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT Non- Port Mode) (1) Rev.4.00 Oct. 10, 2008 Page lii of xcviii REJ09B0370-0400 Revision (See Manual for Details) Table amended and note added HD6417751RBP240 (V), ...
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Item Page 23.3.4 Peripheral 1070 Module Signal Timing Table 23.26 PCIC Signal Timing (in PCIREQ/PCIGNT Non- Port Mode) (2) Table 23.27 PCIC 1072 Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1) Table 23.28 PCIC Signal Timing (With PCIREQ/PCIGNT ...
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Item Page Appendix A Address 1077 to List 1084 Table A.1 Address List 1078 Appendix B Package 1087 Dimensions Figure B.3 Package Dimensions (256-pin BGA) Appendix C Mode Pin 1089 Settings Table C.1 Clock Operating Modes (SH7751) Table C.7 PCI ...
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Item Page D.1 Pin States 1093, 1094 Table D.1 Pin States in Reset, Power-Down State, and Bus- Released State (PCI Enable, Disable Common) Table D.2 Pin States in 1095 Reset, Power-Down State, and Bus- Released State (PCI Enable) Table D.3 ...
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Item Page Appendix H Product 1119 Lineup Table H.1 SH7751/SH7751R Product Lineup Appendix I Version 1121, Registers 1122 All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Oct. 10, 2008 Page lvi of xcviii REJ09B0370-0400 Revision ...
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Section 1 Overview ............................................................................................................. 1.1 SH7751/SH7751R Features .............................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement ............................................................................................................... 10 1.4 Pin Functions .................................................................................................................... 13 1.4.1 Pin Functions (256-Pin QFP)............................................................................... 13 1.4.2 Pin Functions (256-Pin BGA).............................................................................. 24 1.4.3 Pin Functions (292-Pin BGA).............................................................................. 35 ...
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TLB Functions .................................................................................................................. 78 3.4.1 Unified TLB (UTLB) Configuration ................................................................... 78 3.4.2 Instruction TLB (ITLB) Configuration................................................................ 82 3.4.3 Address Translation Method................................................................................ 82 3.5 MMU Functions................................................................................................................ 85 3.5.1 MMU Hardware Management ............................................................................. 85 3.5.2 MMU Software Management .............................................................................. 85 3.5.3 ...
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Coherency between Cache and External Memory ............................................... 113 4.3.9 Prefetch Operation ............................................................................................... 113 4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode .................................................................................................................... 114 4.4 Instruction Cache (IC)....................................................................................................... 116 4.4.1 Configuration ....................................................................................................... 116 4.4.2 ...
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Return from Exception Handling......................................................................... 146 5.6 Description of Exceptions................................................................................................. 146 5.6.1 Resets................................................................................................................... 147 5.6.2 General Exceptions .............................................................................................. 152 5.6.3 Interrupts.............................................................................................................. 166 5.6.4 Priority Order with Multiple Exceptions.............................................................. 169 5.7 Usage Notes ...................................................................................................................... 170 5.8 Restrictions ....................................................................................................................... 171 Section 6 ...
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Section 8 Pipelining ............................................................................................................ 211 8.1 Pipelines............................................................................................................................ 211 8.2 Parallel-Executability........................................................................................................ 218 8.3 Execution Cycles and Pipeline Stalling ............................................................................ 222 8.4 Usage Notes ...................................................................................................................... 238 Section 9 Power-Down Modes 9.1 Overview........................................................................................................................... 239 9.1.1 Types of Power-Down Modes ............................................................................. 239 9.1.2 Register ...
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In Reset ................................................................................................................ 255 9.9.2 In Exit from Standby Mode ................................................................................. 256 9.9.3 In Exit from Sleep Mode...................................................................................... 257 9.9.4 In Exit from Deep Sleep Mode ............................................................................ 260 9.9.5 Hardware Standby Mode Timing......................................................................... 262 9.10 Usage Notes ...................................................................................................................... 264 ...
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Section 11 Realtime Clock (RTC) 11.1 Overview........................................................................................................................... 291 11.1.1 Features................................................................................................................ 291 11.1.2 Block Diagram ..................................................................................................... 292 11.1.3 Pin Configuration................................................................................................. 293 11.1.4 Register Configuration......................................................................................... 293 11.2 Register Descriptions ........................................................................................................ 295 11.2 Counter (R64CNT).................................................................................... 295 11.2.2 Second Counter (RSECCNT) .............................................................................. ...
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Register Configuration......................................................................................... 317 12.2 Register Descriptions ........................................................................................................ 318 12.2.1 Timer Output Control Register (TOCR) .............................................................. 318 12.2.2 Timer Start Register (TSTR) ............................................................................... 319 12.2.3 Timer Start Register 2 (TSTR2)........................................................................... 320 12.2.4 Timer Constant Registers (TCOR) ...................................................................... 321 12.2.5 Timer ...
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Refresh Time Constant Register (RTCOR) ......................................................... 391 13.2.14 Refresh Count Register (RFCR) .......................................................................... 392 13.2.15 Notes on Accessing Refresh Control Registers.................................................... 392 13.3 Operation........................................................................................................................... 393 13.3.1 Endian/Access Size and Data Alignment............................................................. 393 13.3.2 Areas .................................................................................................................... 400 13.3.3 SRAM Interface ...
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Examples of Transfer between External Memory and an External Device with DACK .......................................................................................................... 552 14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 553 14.5.1 Operation ............................................................................................................. 553 14.5.2 Pins in DDT Mode............................................................................................... 555 14.5.3 Transfer Request Acceptance on Each Channel ...
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Bit Rate Register (SCBRR1)................................................................................ 623 15.3 Operation........................................................................................................................... 631 15.3.1 Overview.............................................................................................................. 631 15.3.2 Operation in Asynchronous Mode ....................................................................... 633 15.3.3 Multiprocessor Communication Function............................................................ 644 15.3.4 Operation in Synchronous Mode ......................................................................... 655 15.4 SCI Interrupt Sources and DMAC .................................................................................... 665 15.5 ...
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Register Descriptions ........................................................................................................ 722 17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 722 17.2.2 Serial Mode Register (SCSMR1)......................................................................... 723 17.2.3 Serial Control Register (SCSCR1)....................................................................... 724 17.2.4 Serial Status Register (SCSSR1).......................................................................... 725 17.3 Operation .......................................................................................................................... 726 17.3.1 Overview.............................................................................................................. 726 17.3.2 Pin ...
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Register Descriptions ........................................................................................................ 780 19.3.1 Interrupt Priority Registers (IPRA–IPRD) ............................................... 780 19.3.2 Interrupt Control Register (ICR).......................................................................... 781 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) ................................... 783 19.3.4 Interrupt Factor Register 00 (INTREQ00) ........................................................... 784 19.3.5 ...
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Program Counter (PC) Value Saved .................................................................... 812 20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 813 20.3.9 Usage Notes ......................................................................................................... 814 20.4 User Break Debug Support Function ................................................................................ 816 20.5 Examples of Use ............................................................................................................... 818 20.6 User ...
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PCI Configuration Register 4 (PCICONF4) ........................................................ 867 22.2.6 PCI Configuration Register 5 (PCICONF5) ........................................................ 869 22.2.7 PCI Configuration Register 6 (PCICONF6) ........................................................ 871 22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10) ...................................................................................................... 873 22.2.9 PCI ...
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PCI Commands .................................................................................................... 929 22.3.3 PCIC Initialization ............................................................................................... 930 22.3.4 Local Register Access.......................................................................................... 931 22.3.5 Host Functions ..................................................................................................... 931 22.3.6 PCI Bus Arbitration in Non-host Mode ............................................................... 934 22.3.7 PIO Transfers....................................................................................................... 934 22.3.8 Target Transfers................................................................................................... 937 22.3.9 DMA Transfers ...
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DC Characteristics ............................................................................................................ 982 23.3 AC Characteristics ............................................................................................................ 994 23.3.1 Clock and Control Signal Timing .................................................................... 23.3.2 Control Signal Timing ..................................................................................... 1006 23.3.3 Bus Timing ...................................................................................................... 1010 23.3.4 Peripheral Module Signal Timing.................................................................... 1061 23.3.5 AC Characteristic Test Conditions................................................................... 1074 ...
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Rev.4.00 Oct. 10, 2008 Page lxxiv of xcviii REJ09B0370-0400 ...
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Section 1 Overview Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions......................................... Figure 1.2 Pin Arrangement (256-Pin QFP) ............................................................................ 10 Figure 1.3 Pin Arrangement (256-Pin BGA)........................................................................... 11 Figure 1.4 Pin Arrangement (292-Pin BGA)........................................................................... 12 Section 2 Programming Model Figure 2.1 Data ...
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Figure 4.4 Configuration of Write-Back Buffer ...................................................................... 111 Figure 4.5 Configuration of Write-Through Buffer................................................................. 111 Figure 4.6 Configuration of Instruction Cache (SH7751) ....................................................... 117 Figure 4.7 Configuration of Instruction Cache (SH7751R)..................................................... 118 Figure 4.8 Memory-Mapped IC Address Array ...................................................................... 121 ...
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Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ............................. 260 Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence ................................. 261 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) .......... ...
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Figure 13.8 Example of 16-Bit Data Width SRAM Connection ............................................... 408 Figure 13.9 Example of 8-Bit Data Width SRAM Connection ................................................. 409 Figure 13.10 SRAM Interface Wait Timing (Software Wait Only) ............................................ 410 Figure 13.11 SRAM Interface Wait State Timing ...
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Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) ...... 455 Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM......................................... 456 Figure 13.41 Burst ROM Basic Access Timing .......................................................................... 458 Figure 13.42 ...
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Figure 14.3 Round Robin Mode ................................................................................................ 524 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................... 525 Figure 14.5 Data Flow in Single Address Mode ....................................................................... 527 Figure 14.6 DMA Transfer Timing in Single Address Mode.................................................... 528 ...
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Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD = 1, TRWL = 2, TPC=1).............................................................................. 560 Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ............ 561 Figure 14.29 Single ...
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Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 ............................................. 577 Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel ...
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Figure 15.20 Sample Serial Transmission Flowchart .................................................................. 658 Figure 15.21 Example of SCI Transmit Operation ...................................................................... 660 Figure 15.22 Sample Serial Reception Flowchart (1).................................................................. 661 Figure 15.23 Example of SCI Receive Operation........................................................................ 663 Figure 15.24 Sample Flowchart for Serial Data ...
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Figure 17.13 Procedure for Stopping and Restarting the Clock .................................................. 744 Section 18 I/O Ports Figure 18.1 16-Bit Port A .......................................................................................................... 748 Figure 18.2 16-Bit Port B .......................................................................................................... 749 Figure 18.3 SCK Pin.................................................................................................................. 750 Figure 18.4 TxD Pin .................................................................................................................. 751 ...
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Figure 22.12 Target Write Cycle in Non-Host Mode (Single) .................................................... 954 Figure 22.13 Target Memory Read Cycle in Host Mode (Burst) ................................................ 955 Figure 22.14 Target Memory Write Cycle in Host Mode (Burst) ............................................... 956 Figure 22.15 Master Memory Write ...
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Figure 23.12 (1) Pin Drive Timing for Standby Mode ........................................................... 1008 Figure 23.12 (2) Pin Drive Timing for Software Standby Mode............................................ 1009 Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) ................................................. 1014 Figure 23.14 SRAM Bus Cycle: Basic ...
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Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 ......................................... 1037 Figure 23.36 DRAM Bus Cycle (EDO Mode, ...
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Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) ...... 1056 Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data ...
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Appendix G Power-On and Power-Off Procedures Figure G.1 Method for Temporarily Selecting Clock Operation Mode 6............................. 1117 Figure G.2 Power-On Procedure 1 ....................................................................................... 1118 Figure G.3 Power-On Procedure 2 ....................................................................................... 1118 Rev.4.00 Oct. 10, 2008 Page lxxxix of xcviii REJ09B0370-0400 ...
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Rev.4.00 Oct. 10, 2008 Page xc of xcviii REJ09B0370-0400 ...
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Section 1 Overview Table 1.1 SH7751/SH7751R Features.................................................................................... Table 1.2 Pin Functions.......................................................................................................... 13 Table 1.3 Pin Functions.......................................................................................................... 24 Table 1.4 Pin Functions.......................................................................................................... 35 Section 2 Programming Model Table 2.1 Initial Register Values ............................................................................................ 49 Section 3 Memory Management Unit (MMU) Table ...
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Table 7.11 Floating-Point Control Instructions........................................................................ 206 Table 7.12 Floating-Point Graphics Acceleration Instructions ................................................ 207 Section 8 Pipelining Table 8.1 Instruction Groups.................................................................................................. 218 Table 8.2 Parallel-Executability ............................................................................................. 222 Table 8.3 Execution Cycles.................................................................................................... 229 Section 9 Power-Down Modes Table 9.1 Status of ...
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Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 394 Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 395 Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 396 Table 13.11 32-Bit External Device/Little-Endian Access and ...
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Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................ 629 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 630 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) .................... 630 ...
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Table 19.4 Interrupt Exception Handling Sources and Priority Order ..................................... 777 Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers ........................................... 781 Table 19.6 Interrupt Request Sources and INTPRI00 Register................................................ 783 Table 19.7 Bit Allocation ......................................................................................................... 786 Table 19.8 Interrupt Response ...
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Table 23.10 Clock Timing (HD6417751RF240 (V))................................................................. 994 Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V)) .................... 995 Table 23.12 Clock Timing (HD6417751RF200 (V))................................................................. 995 Table 23.13 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V))............................. 995 Table 23.14 Clock and Control Signal Timing ...
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Appendix D Pin Functions Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common) ......................................................................... 1093 Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable). 1095 Table D.3 Pin States in ...
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Rev.4.00 Oct. 10, 2008 Page xcviii of xcviii REJ09B0370-0400 ...
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SH7751/SH7751R Group Features The SH7751/SH7751R Group microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. The SuperH™* RISC engine is a Renesas original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH™ RISC engine employs ...
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Overview Table 1.1 SH7751/SH7751R Group Features Item Features • LSI Superscalar architecture: Parallel execution of two instructions • External buses (SH buses) ⎯ Separate 26-bit address and 32-bit data buses ⎯ External bus frequency of 1, 1/2, 1/3, 1/4, ...
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Item Features • FPU On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation ...
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Overview Item Features • Clock pulse Choice of main clock generator (CPG) ⎯ SH7751: 1/ times EXTAL ⎯ SH7751R times EXTAL • Clock modes: (Maximum frequency: Varies with models) ⎯ CPU ...
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Item Features • Instruction cache (IC) Cache memory ⎯ 8 Kbytes, direct mapping [SH7751] ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯ 512 entries, ...
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Overview Item Features • Interrupt controller Five independent external interrupts (NMI, IRL3 to IRL0) (INTC) • 15-level signed external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module • User break ...
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Item Features • Direct memory Physical address DMA controller access controller ⎯ SH7751: 4-channel (DMAC) ⎯ SH7751R: 8-channel • Transfer data size: 8, 16, 32 bits bytes • Address modes: ⎯ Single address mode ⎯ Dual ...
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Overview Item Features • PCI bus controller PCI bus controller (supports a subset of PCI revision 2.1)* (PCIC) ⎯ 32-bit bus ⎯ 33 MHz/66 MHz support • PCI master/slave support • PCI host function support ⎯ Built-in bus arbiter ...
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Block Diagram Figure 1.1 shows an internal block diagram of the SH7751/SH7751R Group. CPU I cache CPG INTC SCI (SCIF) RTC TMU PCIC (PCI)DMAC 32-bit PCI address/ data Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions UBC FPU Lower ...
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Overview 1.3 Pin Arrangement XTAL2 193 EXTAL2 194 VDD-RTC 195 VSS-RTC 196 197 CA RESET 198 TRST 199 MRESET 200 NMI 201 BACK/BSREQ 202 BREQ/BSACK 203 MD6/IOIS16 204 RDY 205 206 TXD 207 208 209 210 MD2/RXD2 211 212 ...
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DREQ0 XTAL VDD-PLL1 A EXTAL VDD-PLL2 DRAK1 TDO STATUS1 B CS0 TMS DRAK0 CS1 STATUS0 TCK C CS4 DREQ1 CS6 TDI D BS CS5 ASEBRK/ WE0/REG BRKACK D0 E WE1 ...
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Overview XTAL VDD-PLL1 A EXTAL VSS-CPG VDD-PLL2 TCK VSS-PLL2 B ASEBRK/ VDD-CPG TMS CS0 BRKACK TDO C DREQ1 TDI VSS-PLL1 CS4 D CS1 CS5 BS E CS6 WE0/REG D0 F WE1 ...
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Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions No. Pin Name I/O Function 1 TMS I Mode (H-UDI) 2 TCK I Clock (H-UDI) 3 VDDQ Power IO VDD 4 VSSQ Power IO GND 5 TDI I ...
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Overview No. Pin Name I/O Function 26 D8 I/O Data 27 D9 I/O Data 28 D10 I/O Data 29 VDDQ Power IO VDD 30 VSSQ Power IO GND 31 D11 I/O Data 32 D12 I/O Data 33 D13 I/O ...
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No. Pin Name I/O Function 56 VSSQ Power IO GND Address Address Address Address Address Address 63 A10 O Address 64 A11 ...
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Overview No. Pin Name I/O Function 87 D24 I/O Data 88 D25 I/O Data 89 D26 I/O Data 90 D27 I/O Data 91 D28 I/O Data 92 D29 I/O Data 93 VDDQ Power IO VDD 94 VSSQ Power IO ...
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No. Pin Name I/O Function 116 PCIGNT2 O Bus grant (host function) 117 PCIREQ4 I* Bus request (host function) 118 PCIREQ3/ I* Bus request MD10 (host function)/ mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND 121 PCIREQ2/ ...
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Overview No. Pin Name I/O Function 134 AD28 I/O PCI address/ data/port 135 AD27 I/O PCI address/ data/port 136 AD26 I/O PCI address/ data/port 137 AD25 I/O PCI address/ data/port 138 AD24 I/O PCI address/ data/port 139 C/BE3 I/O ...
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No. Pin Name I/O Function 156 DEVSEL I/O Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND 159 PCISTOP I/O Transaction stop 160 PCILOCK I/O Exclusive access 161 PERR I/O Parity error 162 PAR I/O Parity 163 ...
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Overview No. Pin Name I/O Function 179 AD5 I/O PCI address/ data/port 180 AD4 I/O PCI address/ data/port 181 AD3 I/O PCI address/ data/port 182 AD2 I/O PCI address/ data/port 183 VDDQ Power I/O VDD 184 VSSQ Power I/O ...
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No. Pin Name I/O Function 202 BACK/ O Bus BSREQ acknowledge/ bus request 203 BREQ/ I Bus BSACK request/bus acknowledge 204 MD6/ I Mode/IOIS16 IOIS16 (PCMCIA) 205 RDY I Bus ready 206 TXD O SCI data output 207 VDDQ Power ...
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Overview No. Pin Name I/O Function 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/CE2A I/O Mode/ PCMCIA-CE 231 MD4/CE2B I/O Mode/ PCMCIA-CE ...
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No. Pin Name I/O Function 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG Power CPG VDD ...
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Overview 1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Pin No. Number Pin Name I TMS TCK VDDQ Power 4 F2 VSSQ Power 5 D4 TDI I CS0 6 B1 ...
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Pin No. Number Pin Name I I D10 I VDDQ Power 30 L3 VSSQ Power 31 J2 D11 I D12 I D13 I D14 I ...
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Overview Pin No. Number Pin Name I VSSQ Power A10 O ...
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Pin No. Number Pin Name I D24 I D25 I D26 I D27 I D28 I D29 I/O 93 V10 VDDQ Power 94 W6 VSSQ Power 95 W10 ...
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Overview Pin No. Number Pin Name I/O PCIGNT2 116 U16 O PCIREQ4 1 117 V16 I* PCIREQ3/ 1 118 W16 I* MD10 119 W14 VDDQ Power 120 W15 VSSQ Power PCIREQ2/ 1 121 Y16 I* MD9 122 U17 IDSEL ...
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Pin No. Number Pin Name I/O 136 U20 AD26 I/O 137 T17 AD25 I/O 138 T18 AD24 I/O 139 U19 C/BE3 I/O 140 T20 AD23 I/O 141 R18 AD22 I/O 142 T19 AD21 I/O 143 N19 VDDQ Power 144 W19 ...
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Overview Pin No. Number Pin Name I/O 158 R19 VSSQ Power PCISTOP 159 L20 I/O PCILOCK 160 L19 I/O PERR 161 L17 I/O 162 K20 PAR I/O 163 K18 C/BE1 I/O 164 J20 AD15 I/O 165 J19 AD14 I/O ...
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Pin No. Number Pin Name I/O 180 E19 AD4 I/O 181 E18 AD3 I/O 182 D20 AD2 I/O 183 G19 VDDQ Power 184 K19 VSSQ Power 185 D19 AD1 I/O 186 D18 AD0 I/O IRL0 187 E17 I IRL1 188 ...
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Overview Pin No. Number Pin Name I/O BREQ/ 203 B15 I BSACK 204 C15 MD6/ I IOIS16 RDY 205 A15 I 206 A14 TXD O 207 B14 VDDQ Power 208 F19 VSSQ Power 209 D14 VDD Power 210 D15 ...
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Pin No. Number Pin Name I/O 227 B9 AUDATA2 228 D9 AUDATA3 229 C9 NC 230 A9 MD3/CE2A I/O 231 D8 MD4/CE2B I/O 232 C8 MD5 I 233 C11 VDDQ Power 234 C17 VSSQ Power 235 B8 DACK0 O 236 ...
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Overview Pin No. Number Pin Name I/O 250 B5 VSS-PLL2 Power 251 A4 VDD-PLL1 Power 252 C3 VSS-PLL1 Power 253 A3 VDD-CPG Power 254 B2 VSS-CPG Power 255 A2 XTAL O 256 A1 EXTAL I Legend: I: Input O: ...
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Pin Functions (292-Pin BGA) Table 1.4 Pin Functions Pin No. Number Pin Name I TMS TCK VDDQ Power 4 E4 VSS Power 5 C1 TDI I CS0 CS1 ...
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Overview Pin No. Number Pin Name I I D10 I VDDQ Power 30 D5 VSS Power 31 K2 D11 I D12 I D13 I D14 I/O ...
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Pin No. Number Pin Name I A10 A11 A12 ...
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Overview Pin No. Number Pin Name I D27 I D28 I D29 I VDDQ Power 94 V10 VSS Power 95 Y10 D30 I/O 96 W10 D31 I/O 97 U10 VDD Power ...
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Pin No. Number Pin Name I/O 119 V14 VDDQ Power 120 U16 VSS Power PCIREQ2/ 121 V16 I* MD9 122 Y17 IDSEL I INTA 123 W17 O PCIRST 124 V17 O 125 Y18 PCICLK I PCIGNT1/ 126 W18 O REQOUT ...
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Overview Pin No. Number Pin Name I/O 140 T18 AD23 I/O 141 T19 AD22 I/O 142 R20 AD21 I/O 143 P18 VDDQ Power 144 U12 VDDQ Power 145 P17 VDD Power 146 N17 VSS Power 147 R19 AD20 I/O ...
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Pin No. Number Pin Name I/O 165 J20 AD14 I/O 166 J19 AD13 I/O 167 J18 AD12 I/O 168 H20 AD11 I/O 169 F17 VDDQ Power 170 K17 VSS Power 171 H19 AD10 I/O 172 H18 AD9 I/O 173 G20 ...
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Overview Pin No. Number Pin Name I/O IRL0 187 D18 I IRL1 188 C20 I IRL2 189 C19 I IRL3 190 B20 I 191 B18 VSS-RTC Power 192 E17 VSS Power 193 A20 XTAL2 O 194 A19 EXTAL2 I ...
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Pin No. Number Pin Name I/O 213 A13 TCLK I/O 214 B13 MD8/RTS2 I/O 215 C13 SCK I/O 216 A12 MD1/TXD2 I/O 217 B12 MD0/SCK2 I/O 218 C12 MD7/CTS2 I/O 219 A11 AUDSYNC 220 B11 AUDCK 221 D15 VDDQ Power ...
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Overview Pin No. Number Pin Name I/O 238 B7 DRAK1 O 239 D7 VDD Power 240 D6 VDDQ Power 241 A6 STATUS0 O 242 B6 STATUS1 O DREQ0 243 C6 I DREQ1 244 C5 I ASEBRK/ 245 B5 I/O ...
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Pin No. Number Pin Name I/O 266 N12 VSS Power 267 N13 VSS Power 268 M13 VSS Power 269 L13 VSS Power 270 K13 VSS Power 271 J13 VSS Power 272 H13 VSS Power 273 H12 VSS Power 274 H11 ...
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Overview Notes: Supply power to all power pins. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or ...
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Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH-4 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits) Double-precision floating-point (64 bits ...
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Programming Model 2.2 Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs ...
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Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or ...
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Programming Model BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 ...
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General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one ...
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Programming Model SR. (SR. SR. R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 Programming Note: As ...
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Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and ...
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Programming Model • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR. FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 ...
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Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined ...
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Programming Model • T: True/false condition or carry/borrow bit Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program ...
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Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001 — Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • FR: Floating-point register ...
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Programming Model When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag ...
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Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data ...
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Programming Model The data format in memory is shown in figure 2. Address A Byte 0 Byte 1 Byte 2 Byte 3 15 Address Word 0 31 ...
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See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. ...
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Programming Model 2.7 Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit ...
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32- bit logical (virtual) address space. Address translation from virtual address to physical address is ...
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Memory Management Unit (MMU) manner also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it ...
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Physical Process 1 memory Process 1 Process 1 Process 2 Process 3 3. Memory Management Unit (MMU) Process 1 Physical memory (1) Physical Process 1 memory Process 2 Process 3 (3) Figure 3.1 Role of the MMU Rev.4.00 Oct. 10, ...
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Memory Management Unit (MMU) 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Name tion Page table entry high PTEH register Page table entry low PTEL register Page table entry PTEA assistance ...
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Register Descriptions There are six MMU-related registers. 1. PTEH 31 2. PTEL — — — 3. PTEA 31 4. TTB 31 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. ...
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Memory Management Unit (MMU) 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) ...
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TI: TLB invalidate AT: Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should ...
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Memory Management Unit (MMU) Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and ...
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Address Space 3.3.1 Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this ...
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Memory Management Unit (MMU) CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or ...
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The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store ...
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Memory Management Unit (MMU) 3.3.2 External Memory Space The SH-4 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas relate to memory, such as ...
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Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, ...
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Memory Management Unit (MMU) Here, access to an area of the PCMCIA interface by accessing an area of P1, P2 from the CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with ...
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P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the area, the physical address is uniquely determined without accessing ...
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Memory Management Unit (MMU) with a different ASID and unshared state (SH bit is 0). To avoid this, use workaround (1) or (2) below. (1) Purge the UTLB when switching the ASID values (PTEH and ASID) of the current ...
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Virtual address 31 VPN • 4-Kbyte page Virtual address VPN • 64-Kbyte page Virtual address VPN • 1-Mbyte page Virtual address VPN Figure 3.8 Relationship between Page Size ...
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Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page ...
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C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear ...
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Memory Management Unit (MMU) 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into ...
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Data access to virtual address (VA area in P2 area On-chip I/O access VPNs match and Data TLB miss exception PR R/W? R ...
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Memory Management Unit (MMU area in P2 area 0 Access prohibited No Search UTLB Yes Match? No Instruction TLB miss exception Instruction TLB protection violation exception Figure 3.11 Flowchart of Memory Access Using ...
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MMU Functions 3.5.1 MMU Hardware Management The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. ...
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Memory Management Unit (MMU) issued by a program in the area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR LRUI Entry specification PTEH ...
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UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The ...
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Memory Management Unit (MMU) 3.6 MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection ...
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Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the ...
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Memory Management Unit (MMU) The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. ...
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Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.5 Data TLB Miss Exception ...
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Memory Management Unit (MMU) 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to ...
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Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the ...
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Memory Management Unit (MMU) 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. ...
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Address field Data field Legend: VPN: Virtual page number V: Validity bit E: Entry Figure 3.13 Memory-Mapped ITLB Address Array 3.7.2 ITLB Data Array 1 ITLB data array 1 is ...
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Memory Management Unit (MMU) 31 Address field Data field Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits Figure 3.14 Memory-Mapped ITLB Data Array ...
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Address field Data field Legend: TC: Timing control bit E: Entry Figure 3.15 Memory-Mapped ITLB Data Array 2 3.7.4 UTLB Address Array The UTLB address array is allocated to ...
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Memory Management Unit (MMU) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. ...
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UTLB data array 1 read PPN, V, SZ, PR SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write ...
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Memory Management Unit (MMU) 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 31 Address field ...