R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet
R8A77850ANBGV
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R8A77850ANBGV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7785 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 2008.01 ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100 ...
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This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this ...
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Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Timer/Counter (Compare Match Timer) CPG Clock Pulse Generator CPU Central Processing Unit DDR Double Data Rate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory ...
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MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PCI (local bus) Controller PFC Pin Function Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI ...
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All trademarks and registered trademarks are the property of their respective owners. Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100 ...
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Section 1 Overview .................................................................................................................. 1 1.1 Features of the SH7785.......................................................................................................... 1 1.2 Block Diagram ..................................................................................................................... 13 1.3 Pin Arrangement Table ........................................................................................................ 14 1.4 Pin Arrangement .................................................................................................................. 22 1.5 Physical Memory Address Map ........................................................................................... 24 Section 2 Programming Model 2.1 Data ...
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Exception Event Register (EXPEVT)................................................................... 91 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 92 5.2.4 Non-Support Detection Exception Register (EXPMASK) ................................... 93 5.3 Exception Handling Functions............................................................................................. 95 5.3.1 Exception Handling Flow ..................................................................................... 95 5.3.2 Exception Handling Vector Addresses ................................................................. 95 5.4 Exception ...
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Address Spaces ................................................................................................... 146 7.2 Register Descriptions ......................................................................................................... 152 7.2.1 Page Table Entry High Register (PTEH)............................................................ 153 7.2.2 Page Table Entry Low Register (PTEL) ............................................................. 154 7.2.3 Translation Table Base Register (TTB) .............................................................. 155 7.2.4 TLB Exception Address Register ...
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Overview of 32-Bit Address Extended Mode..................................................... 199 7.8.2 Transition to 32-Bit Address Extended Mode .................................................... 200 7.8.3 Privileged Space Mapping Buffer (PMB) Configuration ................................... 200 7.8.4 PMB Function..................................................................................................... 202 7.8.5 Memory-Mapped PMB Configuration ............................................................... 203 7.8.6 Notes on Using ...
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Store Queues ...................................................................................................................... 238 8.7.1 SQ Configuration................................................................................................ 238 8.7.2 Writing to SQ...................................................................................................... 238 8.7.3 Transfer to External Memory.............................................................................. 239 8.7.4 Determination of SQ Access Exception.............................................................. 240 8.7.5 Reading from SQ ................................................................................................ 240 8.8 Notes on Using 32-Bit Address Extended ...
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Interrupt Sources................................................................................................................ 324 10.4.1 NMI Interrupts.................................................................................................... 324 10.4.2 IRQ Interrupts..................................................................................................... 324 10.4.3 IRL Interrupts ..................................................................................................... 325 10.4.4 On-Chip Peripheral Module Interrupts ............................................................... 327 10.4.5 Priority of On-Chip Peripheral Module Interrupts.............................................. 328 10.4.6 Interrupt Exception Handling and Priority ......................................................... 329 ...
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Bus Arbitration ................................................................................................... 448 11.5.10 Master Mode....................................................................................................... 450 11.5.11 Slave Mode ......................................................................................................... 451 11.5.12 Cooperation between Master and Slave.............................................................. 451 11.5.13 Power-Down Mode and Bus Arbitration ............................................................ 451 11.5.14 Mode Pin Settings and General Input Output Port Settings about ...
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Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc. ................................................................................................ 549 12.5.12 Regarding the Supported Clock Ratio ................................................................ 549 12.5.13 Regarding MCKE Signal Operation ................................................................... 550 Section 13 PCI Controller (PCIC) 13.1 Features.............................................................................................................................. 551 13.2 Input/Output Pins............................................................................................................... 554 ...
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Channel Priority.................................................................................................. 706 14.4.3 DMA Transfer Types.......................................................................................... 709 14.4.4 DMA Transfer Flow ........................................................................................... 717 14.4.5 Repeat Mode Transfer ........................................................................................ 719 14.4.6 Reload Mode Transfer ........................................................................................ 720 14.4.7 DREQ Pin Sampling Timing .............................................................................. 721 14.5 DMAC Interrupt Sources ................................................................................................... 729 ...
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Reset Request ..................................................................................................... 769 16.4.2 Using Watchdog Timer Mode ............................................................................ 771 16.4.3 Using Interval Timer Mode ................................................................................ 771 16.4.4 Time until WDT Counters Overflow.................................................................. 772 16.4.5 Clearing WDT Counters ..................................................................................... 773 16.5 Status Pin Change Timing during Reset ............................................................................ ...
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Timer Control Registers (TCRn ..................................................... 807 18.3.5 Input Capture Register 2 (TCPR2) ..................................................................... 809 18.4 Operation ........................................................................................................................... 810 18.4.1 Counter Operation .............................................................................................. 810 18.4.2 Input Capture Function ....................................................................................... 813 18.5 Interrupts............................................................................................................................ 814 18.6 Usage ...
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Color Palette 4 Transparent Color Register (CP4TR) ........................................ 887 19.3.27 Display Off Mode Output Register (DOOR)...................................................... 890 19.3.28 Color Detection Register (CDER) ...................................................................... 891 19.3.29 Background Plane Output Register (BPOR)....................................................... 892 19.3.30 Raster Interrupt Offset Register (RINTOFSR) ................................................... 894 ...
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Scroll Display ..................................................................................................... 950 19.4.13 Wraparound Display ........................................................................................... 951 19.4.14 Upper-Left Overflow Display............................................................................. 952 19.4.15 Double Buffer Control ........................................................................................ 953 19.4.16 Sync Mode .......................................................................................................... 954 19.5 Display Control.................................................................................................................. 956 19.5.1 Display Timing Generation ................................................................................ 956 19.5.2 CSYNC............................................................................................................... 959 19.5.3 ...
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MC Command FIFO (MCCF) .......................................................................... 1000 20.3.22 MC Status Register (MCSR) ............................................................................ 1003 20.3.23 MC Frame Width Setting Register (MCWR) ................................................... 1004 20.3.24 MC Frame Height Setting Register (MCHR) ................................................... 1005 20.3. Padding Size Setting Register (MCYPR) ...
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Serial Port Register n (SCSPTR) ...................................................................... 1066 21.3.13 Line Status Register n (SCLSR) ....................................................................... 1069 21.3.14 Serial Error Register n (SCRER) ...................................................................... 1070 21.4 Operation ......................................................................................................................... 1071 21.4.1 Overview .......................................................................................................... 1071 21.4.2 Operation in Asynchronous Mode .................................................................... 1074 21.4.3 ...
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Input/Output Pins............................................................................................................. 1153 23.3 Register Descriptions....................................................................................................... 1153 23.3.1 Control Register (SPCR) .................................................................................. 1155 23.3.2 Status Register (SPSR) ..................................................................................... 1158 23.3.3 System Control Register (SPSCR) ................................................................... 1161 23.3.4 Transmit Buffer Register (SPTBR) .................................................................. 1163 23.3.5 Receive Buffer Register (SPRBR).................................................................... 1164 ...
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Operations in MMC Mode................................................................................ 1209 24.5 MMCIF Interrupt Sources................................................................................................ 1239 24.6 Operations when Using DMA.......................................................................................... 1240 24.6.1 Operation in Read Sequence............................................................................. 1240 24.6.2 Operation in Write Sequence ............................................................................ 1250 24.7 Register Accesses with Little Endian Specification......................................................... 1261 Section 25 ...
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Operation ......................................................................................................................... 1314 26.4.1 Bus Format ....................................................................................................... 1314 26.4.2 Non-Compressed Modes .................................................................................. 1315 26.4.3 Compressed Modes........................................................................................... 1324 26.4.4 Operation Modes .............................................................................................. 1327 26.4.5 Transmit Operation........................................................................................... 1328 26.4.6 Receive Operation ............................................................................................ 1331 26.4.7 Serial Clock Control ......................................................................................... 1334 26.5 Usage ...
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Section 28 General Purpose I/O Ports (GPIO) 28.1 Features............................................................................................................................ 1377 28.2 Register Descriptions ....................................................................................................... 1382 28.2.1 Port A Control Register (PACR) ...................................................................... 1386 28.2.2 Port B Control Register (PBCR)....................................................................... 1389 28.2.3 Port C Control Register (PCCR)....................................................................... 1391 28.2.4 Port D ...
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Port L Pull-Up Control Register (PLPUPR)..................................................... 1438 28.2.38 Port M Pull-Up Control Register (PMPUPR)................................................... 1439 28.2.39 Port N Pull-Up Control Register (PNPUPR) .................................................... 1440 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ............................................. 1441 28.2.41 Input-Pin Pull-Up Control Register 2 ...
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Interrupt Source Register (SDINT)................................................................... 1492 30.3.3 Bypass Register (SDBPR) ................................................................................ 1493 30.3.4 Boundary Scan Register (SDBSR) ................................................................... 1493 30.4 Operation ......................................................................................................................... 1503 30.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) ................................................................................................... 1503 30.4.2 TAP Control...................................................................................................... 1505 30.4.3 H-UDI ...
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Appendix ............................................................................................................................ 1627 A. Package Dimensions ........................................................................................................ 1627 B. Mode Pin Settings............................................................................................................ 1628 C. Pin Functions ................................................................................................................... 1631 C.1 Pin States .......................................................................................................... 1631 C.2 Handling of Unused Pins .................................................................................. 1642 D. Turning On and Off Power Supply .................................................................................. 1653 D.1 ...
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The SH7785 incorporates a DDR2-SDRAM interface, a PCI controller, a DMA controller, timers, serial interfaces, audio interfaces, a graphics data translation accelerator (GDTA) that supports YUV data conversion and motion compensation processing, and a display unit (DU) that supports digital ...
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Overview Item Features • CPU Renesas Technology original architecture • 32-bit internal data bus • General-register files: ⎯ Sixteen 32-bit general registers (eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction ...
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Item Features • FPU On-chip floating-point coprocessor • Supports single (32-bit) and double (64-bit) precisions • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to ...
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Overview Item Features • Memory 4-Gbyte address space, 256 address space identifiers (8-bit ASID) management • Supports single virtual memory mode and multiple virtual memory mode unit (MMU) • Multiple page sizes 64, or 256 Kbytes, ...
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Item Features • URAM 128-Kbyte large-capacity memory • Three independent read/write ports • 8-/16-/32-bit access by the CPU or the FPU • 8-/16-/32-bit access by the DMAC • Interrupt controller Nine independent external interrupts: NMI and IRQ7 to IRQ0 (INTC) ...
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Overview Item Features • Local bus state A dedicated Local-bus interface controller (LBSC) ⎯ Controls the external memory space divided into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wait-cycle insertion can be set for each ...
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Item Features • DDR2-SDRAM bus A dedicated DDR2-SDRAM bus interface controller (DBSC) ⎯ Multi-bank support: Supports multi-bank (four banks) operation ⎯ Number of banks: Supports four or eight banks (however, no more than four banks can be opened concurrently) ⎯ ...
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Overview Item Features • PCI bus controller PCI bus controller (supports a subset of revision 2.2) (PCIC) ⎯ 32-bit bus (33 MHz or 66 MHz) • Operation as PCI master/target • Operation in PCI host/normal mode ⎯ Built-in bus ...
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Item Features • Watchdog timer Number of channels: One (WDT) • Single-channel watchdog timer (operation in watchdog-timer or interval-timer mode is selectable) • Selectable reset function: Power-on or manual reset • Timer unit (TMU) Number of channels: Six • 6-channel ...
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Overview Item Features • Display unit (DU) Display plane ⎯ 6 planes (a maximum number at 480 dots x 234 dots) ⎯ 4 planes (a maximum number at 854 dots x 480 dots) ⎯ 3 planes (a maximum number ...
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Item Features • Synchronized serial Number of channels: One (max.) I/O with FIFO • Supports full-duplex operation (SIOF) • Separate 64-byte (32 bits x 16) FIFOs for transmission and reception • Supports the input and output of 8-/16-bit monaural and ...
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Overview Item Features • Serial sound Number of channels: Two (max.) interface (SSI) • Supports transfer of compressed and non-compressed data • Selectable frame size • NAND flash Number of channels: One (max.) memory • Exclusively for NAND-type flash ...
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Block Diagram A block diagram of the SH7785 is given as figure 1.1. 32 bit/16 bit 300 MHz DDR2-SDRAM DDR2-400/600 1 GB max DDR bus ROM 64*/32/16 /8 bit 100 MHz NOR Flash SRAM Local bus PC Card/ATA3 Note: ...
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Overview 1.3 Pin Arrangement Table Table 1.2 Pin Function No. Pin Name I/O Function 1 MDQ0 IO DDR data 0 2 MDQ1 IO DDR data 1 3 MDQ2 IO DDR data 2 4 MDQ3 IO DDR data 3 5 ...
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No. Pin Name I/O Function 55 MA10 O DDR address 10 56 MA11 O DDR address 11 57 MA12 O DDR address 12 58 MA13 O DDR address 13 59 MA14 O DDR address 14 60 MBA0 O DDR bank ...
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Overview No. Pin Name I/O Function 119 A12 O Local bus address 12 120 A13 O Local bus address 13 121 A14 O Local bus address 14 122 A15 O Local bus address 15 123 A16 O Local bus ...
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No. Pin Name I/O Function 155 D37/AD5/DR5 IO/IO/O Local bus data 37/PCI address data 5/Digital red 5 156 D38/AD6/DG0 IO/IO/O Local bus data 38/PCI address data 6/Digital green 0 157 D39/AD7/DG1 IO/IO/O Local bus data 39/PCI address data 7/Digital green ...
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Overview No. Pin Name I/O Function 181 D63/AD31 IO/IO Local bus data 63/PCI address data 31 182 WE4/CBE0 O/IO Write enable 4/PCI command/byte enable 0 183 WE5/CBE1 O/IO Write enable 5/PCI command/byte enable 1 184 WE6/CBE2 O/IO Write enable ...
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No. Pin Name I/O Function 217 BREQ/BSACK I Bus request (Master mode)/ Bus acknowledgement (Slave mode) 218 BACK/BSREQ O Bus acknowledgement (Master mode)/Bus request (Slave mode) 219 DREQ0 I DMA channel 0 request 220 DREQ1 I DMA channel 1 request ...
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Overview No. Pin Name I/O Function 249 SIOF_SCK/ IO/I/IO SIOF serial clock/HAC0 bit HAC0_BITCLK/ clock/SSI0 serial bit clock SSI0_CLK 250 SIOF_MCLK/ I/O SIOF master clock/HAC HAC_RES reset 251 SIOF_SYNC/ IO/O/IO SIOF flame HAC0_SYNC/ synchronous/HAC0 flame SSI0_WS synchronous/SSI0 word select ...
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No. Pin Name I/O Function 269 MODE11/ I/IO/IO Mode control 11/SCIF4 SCIF4_SCK/ serial clock/NAND flash data FD3 3 270 MODE12/ I/O/O Mode control 12/DMA DRAK3/CE2B channel 3 transfer request acknowledge 3/PCMCIA CE2B 271 MODE13/ I/IO/I TMU clock/PCMCIA IOIS16 TCLK/IOIS16 272 ...
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Overview 1.4 Pin Arrangement Package: 436-pin FC-BGA mm, ball pitch: 0 VSS MCK0 VSS MCKE MBA0 MA9 MDQ1 VDD- VDD- MCK0 B MCK1 MA1 VSS MDQ2 DDR ...
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AB VSS A24 A21 A19 A15 A12 A7 AA A25 VDDQ A22 VDDQ A16 VSS A8 SCIF5_TXD SCIF5_RXD /HAC1_ /HAC1_ Y A23 A20 A17 A13 A9 SYNC/SSI1_ SDIN/SSI1_ WS SCK SCIF5_SCK MODE11/ /HAC1_SD W ...
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Overview 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces. For details of mappings from the virtual address space to the physical address spaces, see section 7, ...
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Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1. ...
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Programming Model 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception ...
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Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. (4) System Registers System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register ...
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Programming Model Table 2.1 Initial Register Values Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 R15 Control registers SR GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL Floating-point FR0 to ...
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R0 _ BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 R10 ...
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Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these ...
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Note on Programming: As the user are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt are assigned to R0_BANK1 to R7_BANK1 not necessary for the interrupt handler to save ...
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Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR. FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 ...
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Control Registers (1) Status Register (SR) BIt Initial value R/W: R R/W R/W R/W BIt Initial value R/W: R ...
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Programming Model Initial Bit Bit Name Value — All — All IMASK 1111 3, 2 — All 0 1 ...
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Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value ...
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Programming Model (4) Floating-Point Status/Control Register (FPSCR) BIt Initial value R/ BIt Cause Initial value R/W: R/W R/W R/W R/W Initial Bit Bit Name ...
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Initial Bit Bit Name Value Cause 000000 Enable (EN) 00000 Flag 00000 R/W Description R/W FPU Exception Cause Field FPU Exception Enable Field R/W FPU Exception Flag ...
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Programming Model <Big endian> 63 Floating-point register 63 FR (2i) 63 Memory area 8n <Little endian> 63 Floating-point register 63 FR (2i) 63 Memory area 4n+3 Notes the case and ...
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Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 ...
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Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded into a ...
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Address A Byte 0 15 Address Word 0 31 Address For the 64-bit data format, see figure 2.5. 2.6 Processing States This LSI has major three processing states: the ...
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Programming Model From any state when reset/manual reset input Reset/manual reset clearance Instruction execution state Figure 2.8 Processing State Transitions Rev.1.00 Jan. 10, 2008 Page 42 of 1658 REJ09B0261-0100 Reset state Reset/manual Reset/manual reset input reset input Sleep instruction ...
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Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate the processing speed, the instruction prefetching capability of this LSI has been significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is rewritten ...
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Programming Model Rev.1.00 Jan. 10, 2008 Page 44 of 1658 REJ09B0261-0100 ...
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Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved ...
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Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions BRA ADD : : TARGET target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If ...
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Instruction Set Addressing Instruction Mode Format Register @–Rn indirect with pre- decrement Register @(disp:4, Rn) Effective address is register Rn contents with indirect with displacement Indexed @(R0, Rn) register indirect Rev.1.00 Jan. 10, 2008 Page 48 of 1658 REJ09B0261-0100 ...
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Addressing Instruction Mode Format GBR indirect @(disp:8, with displace- GBR) ment Indexed GBR @(R0, GBR) indirect PC-relative @(disp:8, PC) with displacement Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, ...
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Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method PC-relative disp:8 Effective address with 8-bit displacement disp added after being sign-extended and multiplied by 2. (sign-extended) PC-relative disp:12 Effective address ...
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Addressing Instruction Mode Format Effective Address Calculation Method Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data ...
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Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Instruction OP.Sz SRC, DEST mnemonic Operation notation MSB ...
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Item Format Privileged mode T bit Value of T bit after instruction execution ⎯ New Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Table 3.4 Fixed-Point Transfer Instructions Instruction Operation imm ...
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Instruction Set Instruction MOV.B @(disp*,Rm),R0 MOV.W @(disp*,Rm),R0 MOV.L @(disp*,Rm),Rn MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp*,GBR) MOV.W R0,@(disp*,GBR) MOV.L R0,@(disp*,GBR) MOV.B @(disp*,GBR),R0 MOV.W @(disp*,GBR),R0 MOV.L @(disp*,GBR),R0 MOVA @(disp*,PC),R0 MOVCO.L R0,@Rn MOVLI.L @Rm,R0 ...
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Instruction Operation T → Rn MOVT Rn Rm → swap lower 2 bytes SWAP.B Rm,Rn → → swap upper/lower SWAP.W Rm,Rn words → Rn Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — XTRCT Rm,Rn The assembler of Renesas ...
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Instruction Set Instruction Operation CMP/STR Rm,Rn When any bytes are equal, 1 → T Otherwise, 0 → T 1-step division (Rn ÷ Rm) DIV1 Rm,Rn MSB of Rn → Q, DIV0S Rm,Rn MSB of Rm → M, M^Q → ...
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Instruction Operation MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn NEG Rm,Rn 0 – Rm – T → Rn, NEGC Rm,Rn borrow → – Rm → Rn ...
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Instruction Set Instruction Operation R0 ∧ imm → R0 XOR #imm,R0 (R0 + GBR) ∧ imm → XOR.B #imm, @(R0,GBR) (R0 + GBR) Table 3.7 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL Rn LSB → Rn ...
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Table 3.8 Branch Instructions Instruction Operation When disp × label 4 → PC When nop BF/S label Delayed branch; when disp × ...
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Instruction Set Instruction Operation Rm → SSR LDC Rm,SSR Rm → SPC LDC Rm,SPC Rm → DBR LDC Rm,DBR Rm,Rn_BANK Rm → Rn_BANK ( 0100mmmm1nnn1110 LDC (Rm) → SR → Rm LDC.L ...
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Instruction Operation 1 → S SETS 1 → T SETT SLEEP Sleep or standby SR → Rn STC SR,Rn GBR → Rn STC GBR,Rn VBR → Rn STC VBR,Rn SSR → Rn STC SSR,Rn SPC → Rn STC SPC,Rn SGR ...
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Instruction Set Instruction Operation SYNCO Data accesses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed → SPC, TRAPA #imm SR → SSR, R15 → ...
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Instruction Operation FRn + FRm → FRn FADD FRm,FRn When FRn = FRm, 1 → T FCMP/EQ FRm,FRn Otherwise, 0 → T When FRn > FRm, 1 → T FCMP/GT FRm,FRn Otherwise, 0 → T FRn/FRm → FRn FDIV FRm,FRn ...
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Instruction Set Table 3.12 Floating-Point Control Instructions Instruction Operation Rm → FPSCR LDS Rm,FPSCR Rm → FPUL LDS Rm,FPUL LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 (Rm) → FPUL, Rm+4 → Rm LDS.L @Rm+,FPUL FPSCR → Rn ...
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This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. 4.1 Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of eight stages: instruction fetch (I1/I2/I3), decode ...
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Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation ...
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BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + branch cycles E1/S1 E2/s2 E3/s3 (I1) (1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 4 branch cycles E1/S1 ...
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Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for AND#, ...
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Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles (3-3) TAS.B: 4 issue cycles (3-4) PREF, ...
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Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle (4-2) LDC to DBR/SGR: 4 issue cycles (4-3) LDC to GBR: 1 issue cycle (4-4) LDC to SR: 4 issue cycles + ...
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STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle ...
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Pipelining (5-1) LDS to MACH/L: 1 issue cycle (5-2) LDS.L to MACH/L: 1 issue cycle (5-3) STS from MACH/L: 1 issue cycle (5-4) STS.L from MACH/L: 1 issue cycle I1 ...
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LDS to FPUL: 1 issue cycle (6-2) STS from FPUL: 1 issue cycle (6-3) LDS.L to FPUL: 1 issue cycle (6-4) STS.L from FPUL: 1 issue cycle ...
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Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, ...
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FIPR: 1 issue cycle (6-20) FTRV: 1 issue cycle (6-21) FSRRA: 1 issue cycle (6-22) FSCA: 1 issue cycle Figure 4.2 Instruction Execution ...
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Pipelining 4.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the ...
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Instruction Group FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR Legend: R: Rm/Rn @adr: Address SR1: MACH/MACL/PR SR2: FPUL/FPSCR CR1: GBR/Rp_BANK/SPC/SSR/VBR CR2: CR1/DBR/SGR FR: FRm/FRn/DRm/DRn/XDm/XDn The ...
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Pipelining Table 4.3 Combination of Preceding and Following Instructions EX Following EX No Instruction MT Yes (addr+2) BR Yes LS Yes FE Yes CO Rev.1.00 Jan. 10, 2008 Page 78 of 1658 REJ09B0261-0100 Preceding Instruction (addr ...
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Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the ...
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Pipelining Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Data transfer 1 EXTS.B instructions 2 EXTS.W 3 EXTU.B 4 EXTU.W 5 MOV 6 MOV 7 MOVA 8 MOV.W 9 MOV.L 10 MOV.B 11 MOV.W 12 MOV.L ...
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Functional Category No. Instruction Data transfer 30 MOV.L instructions 31 MOV.B 32 MOV.W 33 MOV.L 34 MOV.B 35 MOV.W 36 MOV.L 37 MOV.B 38 MOV.W 39 MOV.L 40 MOVCA.L 41 MOVCO.L 42 MOVLI.L 43 MOVUA.L 44 MOVUA.L 45 MOVT 46 ...
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Pipelining Functional Category No. Instruction Fixed-point 60 CMP/GT arithmetic 61 CMP/HI instructions 62 CMP/HS 63 CMP/PL 64 CMP/PZ 65 CMP/STR 66 DIV0S 67 DIV0U 68 DIV1 69 DMULS.L 70 DMULU MAC.L 73 MAC.W 74 MUL.L 75 ...
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Functional Category No. Instruction Logical 90 TST instructions 91 TST 92 TST.B 93 XOR 94 XOR 95 XOR.B Shift 96 ROTL instructions 97 ROTR 98 ROTCL 99 ROTCR 100 SHAD 101 SHAL 102 SHAR 103 SHLD 104 SHLL 105 SHLL2 ...
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Pipelining Functional Category No. Instruction Branch 120 JMP instructions 121 JSR 122 RTS System 123 NOP control 124 CLRMAC instruction 125 CLRS 126 CLRT 127 ICBI 128 SETS 129 SETT 130 PREFI 131 SYNCO 132 TRAPA 133 RTE 134 ...
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Functional Category No. Instruction System 150 LDC.L control 151 LDC.L instructions 152 LDS 153 LDS 154 LDS 155 LDS.L 156 LDS.L 157 LDS.L 158 STC 159 STC 160 STC 161 STC 162 STC 163 STC 164 STC 165 STC 166 ...
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Pipelining Functional Category No. Instruction Single- 180 FLDI0 precision 181 FLDI1 floating-point 182 FMOV instructions 183 FMOV.S 184 FMOV.S 185 FMOV.S 186 FMOV.S 187 FMOV.S 188 FMOV.S 189 FLDS 190 FSTS 191 FABS 192 FADD 193 FCMP/EQ 194 FCMP/GT ...
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Functional Category No. Instruction Double- 210 FABS precision 211 FADD floating-point 212 FCMP/EQ instructions 213 FCMP/GT 214 FCNVDS 215 FCNVSD 216 FDIV 217 FLOAT 218 FMUL 219 FNEG 220 FSQRT 221 FSUB 222 FTRC FPU system 223 LDS control 224 ...
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Pipelining Functional Category No. Instruction Graphics 241 FRCHG acceleration 242 FSCHG instructions 243 FPCHG 244 FSRRA 245 FSCA 246 FTRV Rev.1.00 Jan. 10, 2008 Page 88 of 1658 REJ09B0261-0100 Instruction Group FRn FE FPUL,DRn FE XMTRX,FVn ...
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Section 5 Exception Handling 5.1 Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must ...
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Exception Handling Table 5.2 States of Register in Each Operating Mode Register Name TRAPA exception register Exception event register Interrupt event register Non-support detection exception register 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit ...
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Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when ...
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Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: 31 ...
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Non-Support Detection Exception Register (EXPMASK) The non-support detection exception register (EXPMASK) is used to enable or disable the generation of exceptions in response to the use of any of functions listed below. The functions of 1 ...
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Exception Handling Initial Bit Bit Name Value ⎯ All 0 4 MMCAW 1 ⎯ All 0 1 BRDSSLP 1 0 RTEDS 1 Rev.1.00 Jan. 10, 2008 Page 94 of 1658 REJ09B0261-0100 R/W Description R ...
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Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), ...
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Exception Handling 5.4 Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI ...
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Exception Execution Category Mode Exception General Completion Unconditional trap (TRAPA) exception type User break after instruction execution* Interrupt Completion Nonmaskable interrupt type General interrupt request Notes: 1. When UBDE in CBCR = DBR. In other cases, PC ...
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Exception Handling 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one ...
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Yes Reset requested? No Execute next instruction General Yes exception requested? No Yes Interrupt requested? SSR ← SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level (*) PC ← ...
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Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot illegal ...
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Exception Requests and BL Bit When the BL bit general exceptions and interrupts are accepted. When the BL bit and an general exception other than a user break is generated, the ...
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Exception Handling 5.6 Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets (1) Power-On Reset • Condition: Power-on ...
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Instruction TLB Multiple Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 ...
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Exception Handling 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set ...
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Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual ...
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Exception Handling (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this ...
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Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits or EPR bits) shown in table 5.4 and table 5.5. Table 5.4 UTLB Protection Information (TLB Compatible Mode) PR Privileged ...
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Exception Handling The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or ...
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Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits or EPR bits) shown in table 5.6 and table5.7. Table 5.6 ITLB Protection Information (TLB Compatible Mode) PR Privileged Mode ...
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Exception Handling ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR. SR. SR. VBR + H'0000 0100; } ...
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Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. ...
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Exception Handling (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user ...
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Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value ...
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Exception Handling (9) General Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding in ...
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Slot Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding of an instruction that modifies ...
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Exception Handling (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR. • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the ...
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Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in ...
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Exception Handling (13) Pre-Execution User Break/Post-Execution User Break • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, ...
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FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and ...
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Exception Handling 5.6.3 Interrupts (1) NMI (Nonmaskable Interrupt) • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved ...
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The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB bits are set SR, and a branch is made to VBR + H'0600. When the INTMU bit in CPUOPM is ...
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Exception Handling 8. Initial page write exception in second data transfer (2) Indivisible Delayed Branch Instruction and Delay Slot Instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single ...
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Usage Notes (1) Return from Exception Handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit before restoring them. B. Issue an ...
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Exception Handling other exceptions is determined depending on the processing mode by SR after restoring or the BL bit. The completion type exception is accepted before branching to the destination of RTE instruction. However, if the re-execution type exception ...
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Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU has the following features. • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round ...
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Floating-Point Unit (FPU) 6.2 Data Formats 6.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign bit (s) • Exponent field (e) • Fraction field (f) This LSI can handle single-precision and double-precision floating-point numbers, ...
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Table 6.1 Floating-Point Number Formats and Parameters Parameter Single-Precision Total bit width 32 bits Sign bit 1 bit Exponent field 8 bits Fraction field 23 bits Precision 24 bits Bias +127 E +127 max E –126 min Floating-point number value ...
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Floating-Point Unit (FPU) Table 6.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number Rev.1.00 Jan. 10, ...
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Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit ...
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Floating-Point Unit (FPU) See section 10, Instruction Descriptions of the SH-4A Extended Functions Software Manual for details of floating-point operations when a non-number (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is ...
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Register Descriptions 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers comprised with two banks: FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1. These thirty-two registers are referenced as FR0 to FR15, ...
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Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR. FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 ...
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Floating-Point Status/Control Register (FPSCR) bit Initial value R/ bit Cause Initial value R/W: R/W R/W R/W R/W Initial Bit Bit Name Value ...
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Floating-Point Unit (FPU) Initial Bit Bit Name Value Cause All Enable All Flag All 0 1 RM1 0 0 RM0 1 Rev.1.00 Jan. 10, 2008 Page 134 of ...
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Floating-point register DR (2i (2i) FR (2i+ Memory area 8n 8n+3 8n+4 <Little endian> 63 Floating-point register DR (2i (2i) FR (2i+ Memory area 4n+3 4n 4m+3 ...
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Floating-Point Unit (FPU) Table 6.3 Bit Allocation for FPU Exception Handling FPU Field Name Error (E) Cause FPU exception Bit 17 cause field Enable FPU exception None enable field Flag FPU exception None flag field 6.3.3 Floating-Point Communication Register ...
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Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic ...
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Floating-Point Unit (FPU) 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in other than ...
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FPU Exception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR. and a denormalized number is input • Invalid operation (V): FPSCR.Enable and (instruction = FTRV or invalid operation) ...
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Floating-Point Unit (FPU) 6.6 Graphics Support Functions This LSI supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value ...
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FTRV XMTRX, FVn ( 12) This instruction is basically used for the following purposes: • Matrix (4 × 4) ⋅ vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector ...
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Floating-Point Unit (FPU) This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer. Rev.1.00 Jan. 10, 2008 Page 142 of 1658 REJ09B0261-0100 ...
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Section 7 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit or 32-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory ...
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Memory Management Unit (MMU) 7.1 Overview of MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in (0) in figure 7.1, when a process is smaller in size than the physical ...
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There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation ...
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Memory Management Unit (MMU) 7.1.1 Address Spaces (1) Virtual Address Space This LSI supports a 32-bit virtual address space, and can access a 4-Gbyte address space. The virtual address space is divided into a number of areas, as shown ...
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H'0000 0000 P0 area Cacheable Address translation possible H'8000 0000 P1 area Cacheable Address translation not possible H'A000 0000 P2 area Non-cacheable Address translation not possible H'C000 0000 P3 area Cacheable Address translation possible H'E000 0000 P4 area Non-cacheable ...
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Memory Management Unit (MMU) (b) P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits ...
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The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see section 8.7, Store Queues. The area from ...
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Memory Management Unit (MMU) (2) Physical Address Space This LSI supports a 29-bit physical address space. The physical address space is divided into eight areas as shown in figure 7.5. Area reserved area. For details, see ...
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TLB miss exception is re-executed. (4) Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, ...
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Memory Management Unit (MMU) 7.2 Register Descriptions The following registers are related to MMU processing. Table 7.1 Register Configuration Register Name Page table entry high register Page table entry low register Translation table base register TLB exception address register ...
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Register Name Instruction re-fetch inhibit control register 7.2.1 Page Table Entry High Register (PTEH) PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the ...
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Memory Management Unit (MMU) Initial Bit Bit Name Value VPN Undefined R/W ⎯ All ASID Undefined R/W 7.2.2 Page Table Entry Low Register (PTEL) PTEL is used to hold the ...
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Initial Bit Bit Name Value 8 V Undefined R/W 7 SZ1 Undefined R/W 6 PR1 Undefined R/W 5 PR0 Undefined R/W 4 SZ0 Undefined R Undefined R Undefined R Undefined R Undefined ...
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Memory Management Unit (MMU) 7.2.4 TLB Exception Address Register (TEA) After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is stored. The contents of this register can be changed by software. ...
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Bit LRUI Initial value R/W: R/W R/W R/W R/W R/W R/W Bit URC Initial value R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial Bit Bit Name ...
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Memory Management Unit (MMU) Initial Bit Bit Name Value ⎯ 25, 24 All URB 000000 ⎯ 17, 16 All URC 000000 9 SQMD Rev.1.00 Jan. 10, 2008 ...
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Initial Bit Bit Name Value ⎯ All ⎯ 7.2.6 Page Table Entry Assistance Register (PTEA) Bit − − − − Initial ...
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Memory Management Unit (MMU) Initial Bit Bit Name Value ⎯ All EPR Undefined ESZ Undefined ⎯ All 0 7.2.7 Physical Address Space Control Register (PASCR) PASCR ...
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Initial Bit Bit Name Value ⎯ All H'00 R/W Description R Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. R/W ...
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Memory Management Unit (MMU) 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is changed, IRMCR controls whether the instruction fetch is performed again for the next instruction. The specific resource means the part of control registers, ...
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Initial Bit Bit Name Value R/W Description R/W Re-Fetch Inhibit 1 after Register Change When a register allocated in addresses H'FF200000 to H'FF2FFFFF is changed, this bit controls ...
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Memory Management Unit (MMU) 7.3 TLB Functions (TLB Compatible Mode; MMUCR. 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes translate a virtual address to a physical address in a ...
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SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte ...
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Memory Management Unit (MMU) 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been ...
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Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 7.8 shows ...
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Memory Management Unit (MMU area in P2 area 0 1 Data TLB miss exception Data TLB multiple hit exception PR R/W? Data TLB protection violation exception Internal resource ...