UPD78F9212CS-CAB-A

Manufacturer Part NumberUPD78F9212CS-CAB-A
DescriptionMCU 8BIT 4KB FLASH 16PIN
ManufacturerRenesas Electronics America
Series78K0S/Kx1+
UPD78F9212CS-CAB-A datasheet
 


Specifications of UPD78F9212CS-CAB-A

Core Processor78K0SCore Size8-Bit
Speed10MHzPeripheralsLVD, POR, PWM, WDT
Number Of I /o13Program Memory Size4KB (4K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2 V ~ 5.5 VData ConvertersA/D 4x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case*Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Connectivity-
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st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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April 1
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Renesas Electronics Corporation

UPD78F9212CS-CAB-A Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    User’s Manual 78K0S/KY1+ 8-bit Single-Chip Microcontrollers μ PD78F9210 μ PD78F9210(A) μ PD78F9210(A2) μ PD78F9510 Document No. U16994EJ6V0UD00 (6th edition) Date Published November 2009 NS © 2004 Printed in Japan μ PD78F9211 μ PD78F9211(A) μ PD78F9211(A2) μ PD78F9511 μ PD78F9212 μ ...

  • Page 4

    User’s Manual U16994EJ6V0UD ...

  • Page 5

    VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, ...

  • Page 6

    Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a ...

  • Page 7

    Target Readers <R> Purpose Organization How to Use This Manual INTRODUCTION This manual is intended for user engineers who wish to understand the functions of the 78K0S/KY1+ in order to design and develop its application systems and programs. The target ...

  • Page 8

    Conventions Related Documents Documents Related to Devices 78K0S/KY1+ User’s Manual 78K/0S Series Instructions User’s Manual <R> Documents Related to Development Software Tools (User’s Manuals) RA78K0S Ver.2.00 Assembler Package CC78K0S Ver.2.00 C Compiler SM+ System Simulator ID78K0S-QB Ver.3.00 Integrated Debugger PM+ ...

  • Page 9

    Other Related Documents SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See ...

  • Page 10

    CHAPTER 1 OVERVIEW.........................................................................................................................14 1.1 Features .........................................................................................................................................14 1.2 Ordering Information....................................................................................................................16 1.3 Pin Configuration (Top View) ......................................................................................................17 1.3.1 PD78F921x .....................................................................................................................................17 1.3.2 PD78F951x .....................................................................................................................................19 1.4 78K0S/Kx1+ Product Lineup........................................................................................................20 1.5 Block Diagram...............................................................................................................................21 1.5.1 PD78F921x .....................................................................................................................................21 1.5.2 PD78F951x .....................................................................................................................................22 1.6 Functional Outline ........................................................................................................................23 CHAPTER 2 ...

  • Page 11

    Operand Address Addressing .................................................................................................... 50 3.4.1 Direct addressing .............................................................................................................................. 50 3.4.2 Short direct addressing ..................................................................................................................... 51 3.4.3 Special function register (SFR) addressing ....................................................................................... 52 3.4.4 Register addressing .......................................................................................................................... 53 3.4.5 Register indirect addressing.............................................................................................................. 54 3.4.6 Based addressing ............................................................................................................................. 55 ...

  • Page 12

    One-shot pulse output operation .....................................................................................................119 6.5 Cautions Related to 16-bit Timer/Event Counter 00................................................................124 CHAPTER 7 8-BIT TIMER H1 .............................................................................................................131 7.1 Functions of 8-bit Timer H1 .......................................................................................................131 7.2 Configuration of 8-bit Timer H1.................................................................................................131 7.3 Registers Controlling 8-bit Timer H1 ........................................................................................134 ...

  • Page 13

    CHAPTER 11 STANDBY FUNCTION..................................................................................................187 11.1 Standby Function and Configuration .....................................................................................187 11.1.1 Standby function ........................................................................................................................... 187 11.1.2 Registers used during standby...................................................................................................... 189 11.2 Standby Function Operation ...................................................................................................190 11.2.1 HALT mode ................................................................................................................................... 190 11.2.2 STOP mode .................................................................................................................................. 193 CHAPTER 12 RESET FUNCTION ...

  • Page 14

    Flash Memory Programming by Self Programming..............................................................232 16.8.1 Outline of self programming ..........................................................................................................232 16.8.2 Cautions on self programming function .........................................................................................235 16.8.3 Registers used for self programming function ...............................................................................235 16.8.4 Example of shifting normal mode to self programming mode ........................................................242 16.8.5 ...

  • Page 15

    A.4 Debugging Tools (Hardware)....................................................................................................329 A.4.1 When using in-circuit emulator QB-78K0SKX1............................................................................... 329 A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................... 330 A.5 Debugging Tools (Software).....................................................................................................331 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................332 APPENDIX C REGISTER INDEX.........................................................................................................334 C.1 Register ...

  • Page 16

    Features O 78K0S CPU core O ROM and RAM capacities Item Part number <R> PD78F9210, 78F9510 <R> PD78F9211, 78F9511 <R> PD78F9212, 78F9512 O Minimum instruction execution time: 0.2 s (with 10 MHz@4.0 to 5.5 V operation) O Clock High-speed ...

  • Page 17

    O Enhanced development environment Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage 2 Use these products in the following voltage range because the detection voltage (V the supply voltage ...

  • Page 18

    Ordering Information <R> Part Number PD78F9 - - - ( ) " ...

  • Page 19

    Pin Configuration (Top View) 1.3.1 PD78F921x 16-pin plastic SSOP P20/ANI0/TI000/TOH1 P41 P40 Note Note P47 P46 P23/X1/ANI3 16-pin plastic SDIP P21/ANI1/TI010/TO00/INTP0 P20/ANI0/TI000/TOH1 Notes 1. In PD78F921x, V functions alternately as the ground potential ...

  • Page 20

    WLBGA (2.24 1.93) 4 Pin No. A1 P20/ANI0/TI000/TOH1 Note1 P47 A4 P23/X1/ANI3 B1 P41 B2 P40 Note2 P46 Pin Name ANI0 to ANI3: Analog input INTP0, INTP1: External interrupt input P20 ...

  • Page 21

    PD78F951x <R> 16-pin plastic SSOP P20/TI000/TOH1 Pin Name INTP0, INTP1: P20 to P23: P32, P34: P40 to P47: RESET: CHAPTER 1 OVERVIEW 1 P41 2 P40 P47 6 P46 7 P23/X1 8 ...

  • Page 22

    Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number Item Number of pins <R> Internal Flash memory memory RAM Supply voltage Minimum instruction execution time System clock (oscillation frequency) Clock for TMH1 and ...

  • Page 23

    Block Diagram 1.5.1 PD78F921x TO00/TI010/P21 16-bit timer/ event counter 00 TI000/P20 TOH1/P20 8-bit timer H1 Low-speed internal oscillator ANI0/P20 to A/D converter 4 ANI3/P23 INTP0/P21 Interrupt control INTP1/P32 Notes 1. In PD78F921x, V functions alternately as the A/D converter ...

  • Page 24

    PD78F951x TO00/TI010/P21 16-bit timer/ event counter 00 TI000/P20 TOH1/P20 8-bit timer H1 Low-speed internal oscillator Watchdog INTP0/P21 Interrupt control INTP1/P32 22 CHAPTER 1 OVERVIEW 78K0S Flash CPU memory core timer Internal high-speed RAM User’s ...

  • Page 25

    Functional Outline Item <R> Internal Flash memory memory High-speed RAM Memory space X1 input clock (oscillation frequency) Internal High speed (oscillation oscillation frequency) clock Low speed (for TMH1 and WDT) General-purpose registers Instruction execution time I/O port Timer Timer ...

  • Page 26

    Pin Function List 2.1.1 PD78F921x (1) Port pins Pin Name I/O P20 I/O Port 2. 4-bit I/O port. P21 Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting ...

  • Page 27

    Non-port pins Pin Name I/O INTP0 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified INTP1 TI000 Input External count clock input to 16-bit timer/event counter ...

  • Page 28

    PD78F951x (1) Port pins Pin Name I/O P20 I/O Port 2. 4-bit I/O port. P21 Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting Note P22 ...

  • Page 29

    Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to input an analog signal to the A/D ...

  • Page 30

    P32 and P34 (Port 3) P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external interrupt request signal. P34 is a 1-bit input-only ...

  • Page 31

    Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figures 2-1 and 2-2. ...

  • Page 32

    Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 8-A Pull up enable Data Output disable 30 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (1/2) Type 11 Pull up enable Data Output disable Comparator Type 11-H V ...

  • Page 33

    Type 36 OSC enable X1, IN/OUT pullup enable data output disable Comparator + - Comparison voltage pullup enable data output disable Comparator + - Comparison voltage CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/2) Type 36-A feedback ...

  • Page 34

    Memory Space The 78K0S/KY1+ can access memory space. Figures 3-1 to 3-3 show the memory maps. <R> ...

  • Page 35

    Data memory space Program memory space Remark The option byte and protect byte are 1 byte each. CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( PD78F9211, 78F9511 Special function registers (SFR) 256 8 ...

  • Page 36

    Data memory space Program ...

  • Page 37

    Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KY1+ provide the following internal ROMs (or flash memory) containing the following capacities. <R> ...

  • Page 38

    Internal data memory space 128-byte internal high-speed RAM is provided in the 78K0S/KY1+. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware ...

  • Page 39

    Special function registers (SFR Internal high-speed RAM ...

  • Page 40

    Figure 3-6. Data Memory Addressing ( PD78F9212, 78F9512 Special function registers (SFR) 256 Internal ...

  • Page 41

    Processor Registers The 78K0S/KY1+ provide the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, ...

  • Page 42

    Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When the interrupt disabled (DI) status is set. All interrupt requests are disabled. When the interrupt enabled (EI) status ...

  • Page 43

    Figure 3-10. Data to Be Saved to Stack Memory PUSH rp instruction Lower half register pairs Upper half register pairs SP Figure 3-11. Data to Be Restored from Stack Memory ...

  • Page 44

    General-purpose registers A general-purpose register consists of eight 8-bit registers ( and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a ...

  • Page 45

    Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose ...

  • Page 46

    Address Symbol 7 6 FF00H, FF01H FF02H FF03H FF04H P4 P47 P46 FF05H to FF0DH FF0EH CMP01 FF0FH CMP11 FF10H, FF11H FF12H TM00 FF13H FF14H CR000 FF15H FF16H CR010 FF17H FF18H ADCR Note ...

  • Page 47

    Address Symbol 7 FF50H LVIM <LVI ON> FF51H LVIS 0 FF52H, FF53H FF54H RESF 0 FF55H to FF57H FF58H LSRCM 0 FF59H to FF5FH FF60H TMC00 0 FF61H PRM00 ES110 FF62H CRC00 0 FF63H TOC00 0 FF64H to FF6FH ...

  • Page 48

    Address Symbol 7 6 FFA0H PFCMD REG7 REG6 FFA1H PFS 0 0 FFA2H FLPMC 0 PRSEL F4 FFA3H FLCMD 0 0 FFA4H FLAPL FLAP7 FLAP6 FFA5H FLAPH 0 0 FFA6H FLAPHC 0 0 FFA7H FLAPLC FLAP FLAP C7 C6 ...

  • Page 49

    Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...

  • Page 50

    Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions ...

  • Page 51

    Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration ...

  • Page 52

    Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...

  • Page 53

    Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH ...

  • Page 54

    Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H ...

  • Page 55

    Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction ...

  • Page 56

    Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing ...

  • Page 57

    Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...

  • Page 58

    Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt ...

  • Page 59

    Functions of Ports The 78K0S/KY1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports ...

  • Page 60

    Port Configuration Ports consist of the following hardware units. Item Control registers Port mode registers (PM2 to PM4) Port registers (P2 to P4) <R> Port mode control register 2 (PMC2) ( PD78F921x only) Pull-up resistor option registers (PU2 to ...

  • Page 61

    Figure 4-2. Block Diagram of P20 and P21 (1/2) (1) PD78F921x WR PU PU2 PU20, PU21 WR PMC PMC2 PMC20, PMC21 Alternate RD function WR PORT P2 Output latch (P20, P21 PM2 PM20, PM21 Alternate function A/D converter ...

  • Page 62

    PD78F951x WR PU PU2 PU20, PU21 Alternate RD function WR PORT Output latch (P20, P21 PM2 PM20, PM21 Alternate function P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: ...

  • Page 63

    PD78F921x WR PU PU2 PU22 WR PMC PMC2 PMC22 RD WR PORT P2 Output latch (P22 PM2 PM22 A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port ...

  • Page 64

    PD78F951x PORT WR PM P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WR : Write signal 62 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block ...

  • Page 65

    PD78F921x WR PU PU2 PU23 WR PMC PMC2 PMC23 RD WR PORT P2 Output latch (P23 PM2 PM23 A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port ...

  • Page 66

    PD78F951x PORT WR PM P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WR××: Write signal 64 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block ...

  • Page 67

    Port 3 The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port mode register 3 (PM3). When this pin is used as an ...

  • Page 68

    RD Reset RD: Read signal Caution Because the P34 pin functions alternately as the RESET pin used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. ...

  • Page 69

    PORT WR PM P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR : Write signal 4.3 Registers Controlling Port Functions The ports are controlled by the ...

  • Page 70

    Port mode registers (PM2 to PM4) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. ...

  • Page 71

    Port registers (P2 to P4) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read ...

  • Page 72

    Figure 4-10. Format of Port Mode Control Register 2 Address: FF84H, After reset: R/W Symbol 7 6 PMC2 0 0 PMC2n 0 Port/alternate-function (except the A/D converter function) mode 1 A/D converter mode Caution When PMC20 to PMC23 are set ...

  • Page 73

    Pull-up resistor option registers (PU2 to PU4) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, and P40 to P47. By setting PU2 to PU4, an on-chip pull-up resistor can ...

  • Page 74

    Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the ...

  • Page 75

    CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation ...

  • Page 76

    Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization ...

  • Page 77

    Figure 5-1. Block Diagram of Clock Generators Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 System clock oscillation stabilization time counter STOP System clock Note oscillator X1/P23/ANI3 Crystal/ceramic oscillation f X X2/P22/ANI2 External clock input High-speed internal oscillation Option byte ...

  • Page 78

    Registers Controlling Clock Generators The clock generators are controlled by the following four registers. Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) (1) Processor clock ...

  • Page 79

    The fastest instruction of the 78K0S/KY1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. CPU Table 5-2. Relationship between CPU Clock ...

  • Page 80

    Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the ...

  • Page 81

    System Clock Oscillators The following three types of system clock oscillators are available. High-speed internal oscillator: Crystal/ceramic oscillator: External clock input circuit: 5.4.1 High-speed internal oscillator The 78K0S/KY1+ include a high-speed internal oscillator (8 MHz (TYP.)). If the high-speed ...

  • Page 82

    Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (c) Wiring near high fluctuating current CHAPTER 5 CLOCK GENERATORS ...

  • Page 83

    Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by ...

  • Page 84

    Operation of CPU Clock Generator A clock ( supplied to the CPU from the system clock (f CPU oscillators. High-speed internal oscillator: Crystal/ceramic oscillator: External clock input circuit: The system clock oscillator is selected by the option ...

  • Page 85

    CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system ...

  • Page 86

    Crystal/ceramic oscillator If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with ...

  • Page 87

    CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation oscillation stabilization Interrupt HALT Remark PCC: Processor clock control register PPCC: Preprocessor clock control register Power application V > 2.1 V (TYP.) DD Reset by power-on-clear ...

  • Page 88

    External clock input circuit If external clock input is selected by the option byte, the following is possible. High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency ...

  • Page 89

    CHAPTER 5 CLOCK GENERATORS Figure 5-13. Status Transition of Default Start by External Clock Input selected by option byte Interrupt HALT Remark PCC: Processor clock control register PPCC: Preprocessor clock control register Power application V > 2.1 V (TYP.) DD ...

  • Page 90

    Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. Clock to peripheral hardware (f XP Low-speed internal oscillation clock (f (1) Clock to peripheral hardware The clock ...

  • Page 91

    Figure 5-14. Status Transition of Low-Speed Internal Oscillator Can be stopped Clock source of WDT is selected Note by software Low-speed internal oscillator can be stopped LSRSTOP = 1 Low-speed internal oscillator stops Note The clock source of the watchdog ...

  • Page 92

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. Number of counts: 2 ...

  • Page 93

    Configuration of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Timer counter Register Timer input Timer output Control registers <R> Figure 6-1 shows a block diagram of these counters. Capture/compare control register 00 (CRC00) ...

  • Page 94

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value ...

  • Page 95

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 ...

  • Page 96

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or ...

  • Page 97

    Caution 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. 6.3 Registers to Control 16-bit Timer/Event ...

  • Page 98

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H R/W Symbol TMC00 TMC003 TMC003 TMC002 TMC001 Operating mode ...

  • Page 99

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers ...

  • Page 100

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer ...

  • Page 101

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution 6. When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be set with the 1-bit ...

  • Page 102

    Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. <1> Immediately after a system reset high level is input to the TI0n0 pin, the operation of 16-bit timer ...

  • Page 103

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Format of Port Mode Control Register 2 (PMC2) ( PD78F921x only) Address: FF84H After reset: 00H R/W Symbol 7 PMC2 0 PMC2n 0 Port/Alternate-function (except A/D converter) mode 1 A/D converter mode ...

  • Page 104

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Control Register Settings for Interval Timer Operation (a) Capture/compare control register 00 (CRC00 CRC00 ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 (c) ...

  • Page 105

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H Timer operation enabled CR000 N INTTM000 Remark Interval time = ( 0001H to FFFFH (settable ...

  • Page 106

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified ...

  • Page 107

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-16. External Event Counter Configuration Diagram f Noise eliminator XP Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH. Figure 6-17. External ...

  • Page 108

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement ...

  • Page 109

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) Capture/compare control register 00 (CRC00 CRC00 0 0 (b) ...

  • Page 110

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock 0000H 0001H TM00 count value TI000 pin input CR010 capture value INTTM010 ...

  • Page 111

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00 CRC00 (b) Prescaler mode register 00 ...

  • Page 112

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 ...

  • Page 113

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00 CRC00 (b) ...

  • Page 114

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H TI000 pin input CR010 capture value CR000 ...

  • Page 115

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 3 PRM00 0/1 0 ...

  • Page 116

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-28 for the set ...

  • Page 117

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 0/1 (d) 16-bit timer mode control ...

  • Page 118

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic ...

  • Page 119

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00 CRC00 (b) 16-bit timer output control register 00 (TOC00) 7 OSPT00 ...

  • Page 120

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Configuration Diagram of PPG Output Noise TI000/ANI0/ eliminator TOH1/P20 f XP Figure 6-32. PPG Output Operation Timing Count clock TM00 count value ...

  • Page 121

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is ...

  • Page 122

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger ES110 ES100 ES010 PRM00 0/1 0/1 0/1 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit ...

  • Page 123

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value N CR000 set value M OSPT00 INTTM010 ...

  • Page 124

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger ES110 ES100 ES010 PRM00 0/1 0/1 0 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit ...

  • Page 125

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-36. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H CR010 set ...

  • Page 126

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after timer ...

  • Page 127

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The values of 16-bit timer capture/compare registers 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped are not guaranteed. Remark (5) Setting of 16-bit timer ...

  • Page 128

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 <3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the ...

  • Page 129

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Capture Register Data Retention Timing Count clock TM00 count value Edge input INTTM010 Capture read signal CR010 capture value (15) Capture operation <1> If the valid edge of the TI000 pin is ...

  • Page 130

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter ...

  • Page 131

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset high level is input to ...

  • Page 132

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the ...

  • Page 133

    Functions of 8-bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output 7.2 Configuration of 8-bit Timer H1 8-bit timer H1 consists of the following hardware. Item Timer register ...

  • Page 134

    H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder ...

  • Page 135

    H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of 8-bit Timer H Compare Register 01 (CMP01) ...

  • Page 136

    Registers Controlling 8-bit Timer H1 The following four registers are used to control 8-bit timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 2 (PM2) • Port register 2 (P2) • Port mode control ...

  • Page 137

    Figure 7-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> Symbol TMHMD1 TMHE1 CKS12 TMHE1 0 Stop timer count operation (counter is cleared Enable timer count operation (count operation started ...

  • Page 138

    Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the P20/TOH1/TI000/ANI0 pin for timer output, clear PM20, the output latch of P20, and PMC20 to 0. PM2 and PMC2 can be set by a ...

  • Page 139

    Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 7-7. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 TMHMD1 0 0/1 0/1 (ii) ...

  • Page 140

    Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H ≤ CMP01 ≤ FEH) Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 <1> <1> The count operation is enabled by setting ...

  • Page 141

    Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Count clock Count start 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Interval time CHAPTER 7 8-BIT ...

  • Page 142

    Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during ...

  • Page 143

    When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, ...

  • Page 144

    Figure 7-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> TOH1 (TOLEV1 = 1) ...

  • Page 145

    Figure 7-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, ...

  • Page 146

    Figure 7-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) 144 CHAPTER 7 8-BIT TIMER H1 00H 01H ...

  • Page 147

    Figure 7-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H CMP01 02H CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) ...

  • Page 148

    Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) ...

  • Page 149

    Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Note 1 Watchdog timer clock Fixed source Operation after reset Operation starts ...

  • Page 150

    Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Control registers Figure 8-1. Block Diagram of Watchdog Timer 2 Clock 16-bit input counter ...

  • Page 151

    Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock ...

  • Page 152

    Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if “1” and “x” ...

  • Page 153

    Operation of Watchdog Timer 8.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is ...

  • Page 154

    Figure 8-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte WDTE = “ACH” Clear WDT counter. HALT instruction HALT WDT count continues. 152 CHAPTER 8 WATCHDOG TIMER Reset WDT clock Overflow ...

  • Page 155

    Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or system clock. After reset ...

  • Page 156

    Figure 8-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte WDT clock = f X Select overflow time (settable only once). WDTE = “ACH” Clear WDT counter. WDT clock ...

  • Page 157

    Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation ...

  • Page 158

    When the watchdog timer operation clock is the low-speed internal oscillation clock (f instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 operation ...

  • Page 159

    Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following ...

  • Page 160

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) Table 9-1. Sampling Time and A/D Conversion Time Reference Sampling Conversion Note 2 Note 3 Voltage Time Time Note 1 Range V 4.5 V 12/f 36 4.0 V 24/f ...

  • Page 161

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) Figure 9-2 shows the block diagram of A/D converter. Figure 9-2. Block Diagram of A/D Converter ANI0/P20/TI000 TOH1 ANI1/P21/TI010/ TO00/INTP0 ANI2/X2/P22 ANI3/X1/P23 2 ADS1 ADS0 ADCS Analog input channel specification register (ADS) Cautions ...

  • Page 162

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage ...

  • Page 163

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.3 Registers Used by A/D Converter The A/D converter uses the following six registers. A/D converter mode register (ADM) Analog input channel specification register (ADS) 10-bit A/D conversion result register (ADCR) 8-bit A/D ...

  • Page 164

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) Figure 9-3. Format of A/D Converter Mode Register (ADM) Address: FF80H After reset: 00H R/W Symbol <7> 6 ADM ADCS 0 ADCS 0 Stops conversion operation Note 1 1 Starts conversion operation FR2 ...

  • Page 165

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) Notes 3. Set the sampling time as follows Set the A/D conversion time as follows. V ...

  • Page 166

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. ...

  • Page 167

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be ...

  • Page 168

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.4 A/D Converter Operations 9.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for ...

  • Page 169

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) Figure 9-10. Basic Operation of A/D Converter Sampling time A/D converter Sampling operation Undefined SAR ADCR, ADCRH INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode ...

  • Page 170

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D ...

  • Page 171

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification ...

  • Page 172

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ...

  • Page 173

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, ...

  • Page 174

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) ...

  • Page 175

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) 9.6 Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of ...

  • Page 176

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 ...

  • Page 177

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore analog input pin is changed during ...

  • Page 178

    CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY) (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 9-21. Internal Equivalent Circuit of ANIn Pin ANIn Table 9-3. Resistance and Capacitance Values (Reference Values) of ...

  • Page 179

    Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the ...

  • Page 180

    Note 1 Interrupt Type Priority Maskable 1 INTLVI 2 INTP0 3 INTP1 4 INTTMH1 5 INTTM000 6 INTTM010 7 INTAD Reset RESET POC LVI WDT Notes 1. Priority is the vector interrupt servicing priority order when several maskable interrupt requests ...

  • Page 181

    Figure 10-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt IF Interrupt request (B) External maskable interrupt External interrupt mode register (INTM0) Edge Interrupt detector request IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 10.3 ...

  • Page 182

    Table 10-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal INTLVI INTP0 INTP1 INTTMH1 INTTM000 INTTM010 Note INTAD <R> Note PD78F921x only (1) Interrupt request flag register 0 (IF0) An interrupt request flag is set to 1 when the ...

  • Page 183

    Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 to FFH. Address: ...

  • Page 184

    Cautions 1. Be sure to clear bits and Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag ( disable interrupts. After setting the INTM0 ...

  • Page 185

    A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 10-6 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are ...

  • Page 186

    Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) Clock CPU NOP Interrupt If an interrupt request flag ( IF) is set at the last clock of the instruction, the interrupt ...

  • Page 187

    Figure 10-9. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged Main processing INTxx During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgment, the ...

  • Page 188

    Figure 10-9. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1. (Interrupt priority INTP0 > INTP1 > INTTMH1 (refer to Table10-1)) Main ...

  • Page 189

    Standby Function and Configuration 11.1.1 Standby function Table 11-1. Relationship Between Operation Clocks in Each Operation Status Status Note 1 Operation Mode Reset Stopped STOP Oscillating HALT Notes 1. When “Cannot be stopped” is selected for low-speed internal oscillator ...

  • Page 190

    STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, ...

  • Page 191

    Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK ...

  • Page 192

    Standby Function Operation 11.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear ...

  • Page 193

    HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt ...

  • Page 194

    Release by reset signal generation When the reset signal is input, HALT mode is released, and then the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 11-3. ...

  • Page 195

    STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with ...

  • Page 196

    STOP mode release Figure 11-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation ...

  • Page 197

    CHAPTER 11 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request (8-bit timer H1 generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is ...

  • Page 198

    Release by reset signal generation When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-6. STOP Mode Release by Reset signal generation (1) If ...

  • Page 199

    The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit ...

  • Page 200

    Figure 12-1. Block Diagram of Reset Function Set Reset signal of WDT RESET Reset signal of POC Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: ...