UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 168

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

9.4
9.4.1
166
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 1 s or longer.
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set ADCS to 1 and start the conversion operation.
<5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) V
<8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage
<9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A
<10> Comparison is continued in this way up to bit 0 of SAR.
<11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.
Cautions 1. Make sure the period of <1> to <4> is 1 s or more.
Remark The following two types of A/D conversion result registers can be used.
A/D Converter Operations
Basic operations of A/D converter
(<5> to <11> are operations performed by hardware.)
input analog voltage is held until the A/D conversion operation has ended.
by the tap selector.
comparator. If the analog input is greater than (1/2) AV
input is smaller than (1/2) V
converter voltage tap is selected according to the preset value of bit 9, as described below.
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, start from <2>.
Bit 9 = 1: (3/4) V
Bit 9 = 0: (1/4) V
Analog input voltage
Analog input voltage < Voltage tap: Bit 8 = 0
2.
ADCR (16 bits): Stores a 10-bit A/D conversion value.
ADCRH (8 bits): Stores an 8-bit A/D conversion value.
It is no problem if the order of <1> and <2> is reversed.
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CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY)
Voltage tap: Bit 8 = 1
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, the MSB is reset to 0.
User’s Manual U16994EJ6V0UD
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, the MSB of SAR remains set to 1. If the analog
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