UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 177

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

(9) A/D conversion result register (ADCR, ADCRH) read operation
(7) Interrupt request flag (ADIF)
(8) Conversion results just after A/D conversion start
(10) Operating current at conversion waiting mode
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Remarks 1. n = 0 to 3
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
When a write operation is performed to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion
result following conversion completion before writing to ADM and ADS. Using a timing other than the above may
cause an incorrect conversion result to be read.
The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion
waiting mode (only the comparator consumes power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter
mode register (ADM) are set to 0 and 1 respectively.
A/D conversion
ADCRH
ADCR,
ADIF
2. m = 0 to 3
ADS rewrite
(start of ANIn conversion)
Figure 9-20. Timing of A/D Conversion End Interrupt Request Generation
ANIn
CHAPTER 9 A/D CONVERTER ( PD78F921x ONLY)
ADS rewrite
(start of ANIm conversion)
User’s Manual U16994EJ6V0UD
ANIn
ANIn
ANIm
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIm
ANIm
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