UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 291

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UPD78F9212CS-CAB-A

Manufacturer Part Number
UPD78F9212CS-CAB-A
Description
MCU 8BIT 4KB FLASH 16PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9212CS-CAB-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Remark
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
!addr16
[addr5]
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
Operand
CHAPTER 18 INSTRUCTION SET OVERVIEW
Bytes
3
1
1
1
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
1
3
3
1
1
User’s Manual U16994EJ6V0UD
Clocks
10
10
10
10
10
10
6
8
6
8
2
4
4
6
8
6
6
6
6
6
6
6
6
8
8
6
6
8
2
6
6
2
2
PC
(SP
PC
PC
PC
PSW
(SP
(SP
PSW
rp
SP
AX
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
B
C
(saddr)
PC
IE
IE
Set HALT Mode
Set STOP Mode
(SP
PC
PC
PC
PC
No Operation
H
H
L
H
H
H
B
C
1 (Enable Interrupt)
0 (Disable Interrupt)
1)
1)
1)
1)
(SP + 1), rp
AX
SP
addr16, SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
PC + 4 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 4 + jdisp8 if (saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW.bit = 0
PC + 3 + jdisp8 if (saddr)
(00000000, addr5), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
A, PC
CPU
(SP + 2), SP
(SP), SP
1, then PC
1, then PC
(saddr)
) selected by the processor clock control register
(PC + 3)
(PC + 1)
PSW, SP
rp
L
H
, (SP
X
L
H
H
Operation
L
L
1, then
SP + 1
, (SP
, (SP
SP
2)
(SP), SP
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
(SP), SP
(SP),
SP + 3, NMIS
SP
2
rp
2)
2)
L
1
, SP
SP
0
(PC + 3)
(PC + 1)
SP + 2
SP + 2
SP
2
0
L
L
,
,
2
0
0
R
Z
R
Flag
AC CY
R
R
289
R
R

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