UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 343

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UPD78F9212CS-CAB-A

Manufacturer Part Number
UPD78F9212CS-CAB-A
Description
MCU 8BIT 4KB FLASH 16PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9212CS-CAB-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
16-bit
timer/
event
counter
00
Function
TOC00: 16-bit
timer output
control register
00
PRM00:
Prescaler mode
register 00
Interval timer
External event
counter
Details of
Function
Timer operation must be stopped before setting other than OSPT00.
If LVS00 and LVR00 are read, 0 is read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.
When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-bit
memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be
set with the 1-bit memory manipulation instruction.
Always set data to PRM00 after stopping the timer operation.
If the valid edge of the TI000 pin is to be set as the count clock, do not set the
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of 16-bit timer counter 00 (TM00) is enabled
→If the rising edge or both rising and falling edges are specified as the valid edge
<2> If the TM00 operation is stopped while the TI0n0 pin is at high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
→If the falling edge or both rising and falling edges are specified as the valid
<3> If the TM00 operation is stopped while the TI0n0 pin is at low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
→If the rising edge or both rising and falling edges are specified as the valid edge
The sampling clock used to eliminate noise differs when the valid edge of TI000 is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a
timer output pin (TO00). When using P21 as the timer output pin (TO00), it
cannot be used as the input pin (TI010) of the valid edge.
Changing the CR000 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
When reading the external event counter count value, TM00 should be read.
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
edge of the TI0n0 pin, a falling edge is detected immediately after the TM00
operation is enabled.
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16994EJ6V0UD
XP
, and in the latter case the count clock is selected by
Cautions
pp. 100,
129
pp. 100,
129
pp. 100,
129
pp. 105,
129
pp. 98,
125
pp. 98,
125
pp. 98,
125
pp. 98,
125
pp. 98,
125
p. 99
pp. 99,
125
pp. 99,
127
p. 101
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