UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 344

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UPD78F9212CS-CAB-A

Manufacturer Part Number
UPD78F9212CS-CAB-A
Description
MCU 8BIT 4KB FLASH 16PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9212CS-CAB-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
342
16-bit
timer/
event
counter
00
Function
Pulse width
measurement
Square-wave
output
PPG output
One-shot pulse
output: software
trigger
One-shot pulse
output: external
trigger
Timer start
errors
One-shot pulse
output
Capture
operation
Details of
Function
To use two capture registers, set the TI000 and TI010 pins.
The measurable pulse width in this operation example is up to 1 cycle of the timer
counter.
Changing the CR000 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
Changing the CRC0n0 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
Values in the following range should be set to CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
The cycle of the pulse generated through PPG output (CR000 setting value + 1)
has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin. Because the external trigger is valid even in this case, the timer is
cleared and started even at the level of the TI000 pin or its alternate-function port
pin, resulting in the output of a pulse at an undesired timing.
Do not set 0000H to the CR000 and CR010 registers.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
Do not input the external trigger again while the one-shot pulse is output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not set the CR000 and CR010 registers to 0000H.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC002 and TMC003 bits.
An error of up to one clock may occur in the time required for a match signal to be
generated after timer start. This is because 16-bit timer counter 00 (TM00) is
started asynchronously to the count clock.
One-shot pulse output normally operates only in the free-running mode or in the
clear & start mode at the valid edge of the TI000 pin. Because an overflow does
not occur in the clear & start mode on a match between TM00 and CR000, one-
shot pulse output is not possible.
When the CRC001 bit value is 1, capture is not performed in the CR000 register if
both the rising and falling edges have been selected as the valid edges of the
TI000 pin.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input from
the TI010 pin can be used as an external interrupt source because INTTM000 is
generated at that timing.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16994EJ6V0UD
Cautions
108, 110,
112
pp. 106,
127
pp. 106,
p. 114
p. 116
pp. 117,
129
pp. 117,
129
pp. 119,
125
pp. 119,
125
pp. 120,
122
pp. 121,
124
pp. 121,
126
pp. 122,
126
pp. 123,
124
p. 124
p. 125
p. 127
p. 127
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