UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 347

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

A/D
converter
(
21x only)
Function
μ
PD78F9
PMC2: Port
mode control
register 2
A/D converter
operations
Operating
current in STOP
mode
Input range of
ANI0 to ANI3
Conflicting
operations
Noise
countermeasures
ANI0/P20 to
ANI3/P23
Details of
Function
If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1,
P21/ANI1/TI010/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for
any purpose other than the A/D converter function. Be sure to set the pull-up
resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter
mode.
Make sure the period of <1> to <4> is 1
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, ignore the data resulting from the first conversion
after <4> in this case.
The period from <5> to <8> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set
using FR2 to FR0.
To satisfy the DC characteristics of the supply current in the STOP mode, clear bit
7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before
executing the STOP instruction.
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of V
higher and V
to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
ADCR, ADCRH read has priority. After the read operation, the new conversion
result is written to ADCR, ADCRH.
ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
To maintain the 10-bit resolution, attention must be paid to noise input to the V
pin and ANI0 to ANI3 pins.
<1> Connect a capacitor with a low equivalent resistance and a high frequency
<2> Because the effect increases in proportion to the output impedance of the
<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their
<4> The conversion accuracy can be improved by setting HALT mode
The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not
access P20 to P23 while conversion is in progress; otherwise the conversion
resolution may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
analog input source, it is recommended that a capacitor be connected
externally, as shown in Figure 9-19, to reduce noise.
alternate functions during conversion.
immediately after the conversion starts.
response to the power supply.
APPENDIX D LIST OF CAUTIONS
SS
User’s Manual U16994EJ6V0UD
or lower (even in the range of absolute maximum ratings) is input
Cautions
μ
s or more.
DD
or
DD
p. 165
pp. 166,
170
pp. 166,
170
p. 170
p. 170
p. 173
p. 173
p. 173
p. 173
p. 173
p. 174
p. 174
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