UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 349

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Interrupt
functions
Standby
function
Reset
function
Function
Interrupt
request pending
STOP mode
STOP mode,
HALT mode
STOP mode
OSTS:
Oscillation
stabilization
time select
register
HALT mode
setting and
operating
statuses
STOP mode
setting and
operating
statuses
Timing of reset
by overflow of
watchdog timer
Details of
Function
−
−
Multiple interrupts can be acknowledged even for low-priority interrupts.
The LSRSTOP setting is valid only when “Can be stopped by software” is set for
the low-speed internal oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware that
operates on the low-speed internal oscillation clock).
The following sequence is recommended for operating current reduction of the
A/D converter in
(ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop
the A/D conversion operation, and then execute the HALT or STOP instruction.
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 11-1).
To set and then release the STOP mode, set the oscillation stabilization time as
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
set by OSTS
The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset signal generation or
interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
clear, the standby mode is immediately cleared if set.
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, in the STOP mode,
the normal operation mode is restored after the STOP instruction is executed and
then the operation is stopped for 34
stabilizing the oscillation set by the oscillation stabilization time select register
(OSTS) has elapsed when crystal/ceramic oscillation is used).
For an external reset, input a low level for 2
During reset signal generation, the system clock and low-speed internal
oscillation clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KY1+ is
reset if a low level is input to the RESET pin after reset is released by the POC
circuit, the LVI circuit and the watchdog timer and before the option byte is
referenced again. The reset status is retained until a high level is input to the
RESET pin.
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
The watchdog timer is also reset in the case of an internal reset of the watchdog
timer.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16994EJ6V0UD
μ
PD78F921x when the standby function is used: First clear bit 7
μ
Cautions
s (TYP.) (after an additional wait time for
μ
s or more to the RESET pin.
p. 185
p. 187
p. 188
p. 188
p. 188
p. 189
p. 189
p. 189
p. 190
p. 193
p. 197
p. 197
p. 197
p. 198
p. 200
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