UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet
UPD78F0550MA-FAA-AX
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Preliminary User’s Manual 78K0/Kx2-L 8-Bit Single-Chip Microcontrollers 78K0/KY2-L: PD78F0550, 78F0551, 78F0552, 78F0555, 78F0556, 78F0557 78K0/KA2-L: PD78F0560, 78F0561, 78F0562, 78F0565, 78F0566, 78F0567 78K0/KB2-L: PD78F0571, 78F0572, 78F0573, 78F0576, 78F0577, 78F0578 78K0/KC2-L: PD78F0581, 78F0582, 78F0583, 78F0586, 78F0587, 78F0588 Document No. U19111EJ2V1UD00 (2nd edition) ...
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Preliminary User’s Manual U19111EJ2V1UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is a trademark of NEC Electronics Corporation. Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the ...
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Caution: This product uses SuperFlash The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/Kx2-L microcontrollers and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KY2-L: PD78F0550, 78F0551, 78F0552, 78F0555, ...
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Conventions Data significance: Active low representations: Note: Caution: Remark: Numerical representations: Binary Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices 78K0/Kx2-L User’s Manual ...
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Documents Related to Development Tools (Hardware) (User’s Manual) QB-MINI2 On-Chip Debug Emulator with Programming Function Documents Related to Flash Memory Programming (User’s Manual) PG-FP5 Flash Memory Programmer Other Documents SEMICONDUCTOR SELECTION GUIDE Semiconductor Device Mount Manual Quality Grades on NEC ...
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CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 Features ........................................................................................................................................ 17 1.2 Ordering Information ................................................................................................................... 19 1.3 Pin Configuration (Top View)...................................................................................................... 21 1.3.1 78K0/KY2-L .....................................................................................................................................21 1.3.2 78K0/KA2-L .....................................................................................................................................22 1.3.3 78K0/KB2-L .....................................................................................................................................23 1.3.4 78K0/KC2-L .....................................................................................................................................24 1.4 Block Diagram .............................................................................................................................. 28 1.4.1 78K0/KY2-L .....................................................................................................................................28 ...
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Special function registers (SFRs).................................................................................................... 83 3.3 Instruction Address Addressing................................................................................................. 88 3.3.1 Relative addressing......................................................................................................................... 88 3.3.2 Immediate addressing..................................................................................................................... 89 3.3.3 Table indirect addressing ................................................................................................................ 90 3.3.4 Register addressing ........................................................................................................................ 91 3.4 Operand Address Addressing .................................................................................................... 91 3.4.1 Implied addressing .......................................................................................................................... ...
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Controlling Clock ....................................................................................................................... 193 5.6.1 Example of controlling high-speed system clock ...........................................................................193 5.6.2 Example of controlling internal high-speed oscillation clock ..........................................................196 5.6.3 Example of controlling subsystem clock ........................................................................................199 5.6.4 Example of controlling internal low-speed oscillation clock............................................................201 5.6.5 Clocks supplied ...
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Operation as PWM output ..............................................................................................................319 8.4.3 Carrier generator operation (8-bit timer H1 only)............................................................................325 CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 332 9.1 Functions of Watchdog Timer................................................................................................... 332 9.2 Configuration of Watchdog Timer ............................................................................................ 333 9.3 Register Controlling Watchdog Timer...................................................................................... 334 9.4 ...
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Operational Amplifier Operations .......................................................................................... 407 13.4.1 Single AMP mode (operational amplifiers 0 and 1) ......................................................................407 13.4.2 PGA (Programmable gain amplifier) mode (operational amplifier 0 only) ....................................407 CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 408 14.1 Functions of Serial Interface UART6...................................................................................... ...
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I/O mode ..................................................................................................................538 CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................ 551 17.1 Interrupt Function Types ......................................................................................................... 551 17.2 Interrupt Sources and Configuration ..................................................................................... 551 17.3 Registers Controlling Interrupt Functions............................................................................. 556 17.4 Interrupt Servicing Operations ............................................................................................... 581 17.4.1 Maskable interrupt ...
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Registers Controlling Regulator............................................................................................. 644 CHAPTER 24 OPTION BYTE............................................................................................................... 646 24.1 Functions of Option Bytes ...................................................................................................... 646 24.2 Format of Option Byte ............................................................................................................. 647 CHAPTER 25 FLASH MEMORY.......................................................................................................... 652 25.1 Internal Memory Size Switching Register.............................................................................. 652 25.2 Writing with Flash ...
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CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS (PRELIMINARY) ............................. 712 CHAPTER 31 CAUTIONS FOR WAIT................................................................................................. 713 31.1 Cautions for Wait...................................................................................................................... 713 31.2 Peripheral Hardware That Generates Wait ............................................................................ 714 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 715 A.1 Software Package ...................................................................................................................... 718 A.2 Language Processing ...
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Features 78K0 CPU core I/O ports, ROM and RAM capacities Item Products 78K0/KY2-L (16 pins) 78K0/KA2-L (20 pins) 78K0/KB2-L (30 pins) 78K0/KC2-L (44 pins) 78K0/KC2-L (48 pins) <R> Low power consumption (V Internal high-speed oscillation mode: STOP mode: Subsystem ...
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Serial interface UART … Asynchronous 2-wire serial interface <R> IICA … Clock synchronous 2-wire serial interface, multimaster supported, standby can be released upon address match in slave mode CSI … Clock synchronous 3-wire serial interface Item Products 78K0/KY2-L (16 pins) ...
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Ordering Information <R> [Part Number] PD78F05 Product Type F Flash memory version [Example of Part Number] PD78F05 5 0 MA-FAA -AX CHAPTER 1 OUTLINE -AX -AX Lead- free MA-FAA 6 MC-CAA 7 MC-CAB ...
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Part Number] 78K0/Kx2-L Package Microcontrollers 78K0/KY2-L 16-pin plastic SSOP (5.72 mm (225)) 78K0/KA2-L 20-pin plastic SSOP (7.62 mm (300)) 78K0/KB2-L 30-pin plastic SSOP (7.62 mm (300)) 78K0/KC2-L 44-pin plastic LQFP (10x10) 48-pin plastic LQFP (fine pitch) (7x7) 20 ...
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Pin Configuration (Top View) 1.3.1 78K0/KY2-L <R> 16-pin plastic SSOP (5.72 mm (225)) P60/SCLA0/TxD6 P61/SDAA0/RxD6 RESET/P125 P122/X2/EXCLK/TOOLD0 P121/X1/TOOLC0 Note AMP0- , AMP0+ Note AMP0OUT : Note PGAIN : ANI0 to ANI3 : AV : REF EXCLK : INTP0, INTP1 ...
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SSOP (7.62 mm (300)) ANI5/P25 ANI4/P24 P60/SCLA0/TxD6 P61/SDAA0/RxD6 RESET/P125 P122/X2/EXCLK/TOOLD0 P121/X1/TOOLC0 REGC V V Note Note AMP0- , AMP0+ : Note AMP0OUT : Note PGAIN : ANI0 to ANI5 : AV : REF EXCLK : ...
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SSOP (7.62 mm (300)) ANI1/P21/AMP0OUT Note Note AMP0- , AMP0+ , Note Note AMP1- , AMP1+ Note AMP0OUT , Note AMP1OUT : Note PGAIN : ANI0 to ANI3, ANI8 to ANI10 : AV : REF ...
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LQFP (10x10) (1/2) P41/RTC1HZ(/SI11) P40/RTCCL/RTCDIV(/SCK11) RESET/P125 P124/XT2/EXCLKS P123/XT1 IC P122/X2/EXCLK/TOOLD0 P121/X1/TOOLC0 REGC Note PD78F0586, 78F0587, 78F0588 (products with operational amplifier) only Cautions 1. Connect the IC (Internally Connected) pin directly ...
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LQFP (10x10) (2/2) Note Note AMP0- , AMP0+ , Note Note AMP1- , AMP1+ : Amplifier Input Note AMP0OUT , Note AMP1OUT : Amplifier Output Note PGAIN : Programmable Gain Amplifier Input ANI0 to ANI10 : Analog ...
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LQFP (fine pitch) (7x7) (1/2) P60/SCLA0/SCK11/INTP11 P61/SDAA0/SI11/INTP10 P62/SO11/INTP9 P63/INTP8 P33/TI51/TO51/INTP4 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P32/INTP3/TOOLD1 Note PD78F0586, 78F0587, 78F0588 (products with operational amplifier) only Cautions 1. Connect the IC (Internally Connected) pin directly to V ...
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LQFP (fine pitch) (7x7) (2/2) Note Note AMP0- , AMP0+ , Note Note AMP1- , AMP1+ : Amplifier Input Note AMP0OUT , Amplifier Output Note AMP1OUT : Note PGAIN : Programmable Gain Amplifier Input ANI0-ANI10 : Analog ...
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Block Diagram <R> 1.4.1 78K0/KY2-L TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 RxD6/P61<LINSEL> TI51/P30 TOH1/P30 8-bit TIMER H1 WATCHDOG TIMER SERIAL RxD6/P61 INTERFACE UART6 TxD6/P60 SDAA0/P61 SERIAL INTERFACE IICA SCLA0/P60 AV REF A/D CONVERTER ANI0/P20 to ANI3/P23 4 Note ...
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TO00/TI010/P01 TI000/P00 RxD6/P61<LINSEL> TI51/P30 TOH1/P30 RxD6/P61 TxD6/P60 SDAA0/P61 SCLA0/P60 AV REF ANI0/P20 to ANI5/P25 Note Note AMP0OUT /PGAIN /P21 Note AMP0+ /P22 Note AMP0- /P20 RxD6/P61<LINSEL> INTP0/P00 INTP1/P30, INTP2/P31, INTP3/P32 Note PD78F0565, 78F0566, 78F0567 (products with operational ...
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TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 RxD6/P14<LINSEL> 8-bit TIMER/ TI50/TO50/P17 EVENT COUNTER 50 8-bit TIMER/ TI51/TO51/P33 EVENT COUNTER 51 TOH0/P15 8-bit TIMER H0 TOH1/P16 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER SERIAL RxD6/P14 INTERFACE UART6 ...
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TO00/TI010/P01 TI000/P00 RxD6/P14 <LINSEL> TI50/TO50/P17 TI51/TO51/P33 TOH0/P15 TOH1/P16 RTCCL/RTCDIV/P40 RTC1HZ/P41 RxD6/P14 TxD6/P13 SDAA0/P61 SCLA0/P60 SCK10/P10 SI10/P11 SO10/P12 SCK11/P60 (SCK11/) P40 SI11/P61 (SI11/) P41 SO11/P62 (SO11/) P120 Note 1 Note 1 SSI11 /P42 AV REF AV SS ANI0/P20 ...
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Outline of Functions Item Internal Flash memory memory (self-programming supported ) 384 bytes to 768 bytes High-Speed RAM Memory space 64 KB <R> High-speed system MHz: V (crystal/ceramic oscillation, external clock ...
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Item Serial UART interface IICA <R> CSI <R> 10-bit A/D converter Operational amplifier (Products with operational amplifier) <R> Vectored interrupt Internal Internal sources External Key interrupt Reset On-chip debug function Power supply voltage Operating ambient temperature Package Note The 48-pin ...
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Pin Function List There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply AV REF V DD Note 78K0/KY2-L: P20 to P23 78K0/KA2-L: P20 to P25 78K0/KB2-L: P20 to ...
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Port functions: 78K0/KY2-L Function Name I/O P00 I/O P01 P20 I/O P21 P22 P23 P30 I/O <R> P60 I/O <R> P61 P121 Input P122 P125 Note PD78F0555, 78F0556, and 78F0557 (products with operational amplifier) only CHAPTER 2 ...
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Non-port functions : 78K0/KY2-L Function Name I/O ANI0 Input A/D converter analog input ANI1 ANI2 ANI3 Note AMP0- Input Operational amplifier 0 input Note AMP0+ Note AMP0OUT Output Operational amplifier 0 output Note PGAIN Input PGA (programmable gain amplifier) ...
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Port functions: 78K0/KA2-L Function Name I/O P00 I/O P01 P20 I/O P21 P22 P23 P24 P25 P30 I/O P31 P32 <R> P60 I/O <R> P61 P121 Input P122 P125 Note PD78F0565, 78F0566, and 78F0567 (products with operational ...
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Non-port functions : 78K0/KA2-L (2/2) Function Name I/O Note AMP0- Input Operational amplifier 0 input Note AMP0+ Note AMP0OUT Output Operational amplifier 0 output Note PGAIN Input PGA (programmable gain amplifier) input INTP0 Input External interrupt request input for ...
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Port functions: 78K0/KB2-L Function Name I/O P00 I/O P01 P10 I/O P11 P12 P13 P14 P15 P16 P17 P20 I/O P21 P22 P23 P30 I/O P31 P32 P33 P60 I/O P61 P120 I/O P121 Input P122 ...
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Non-port functions : 78K0/KB2-L (1/2) Function Name I/O ANI0 Input A/D converter analog input ANI1 ANI2 ANI3 ANI8 ANI9 ANI10 Note AMP0- Input Operational amplifier 0 input Note AMP0+ Note AMP1- Operational amplifier 1 input Note AMP1+ Note AMP0OUT ...
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Non-port functions : 78K0/KB2-L (2/2) Function Name I/O SCK10 I/O Clock input/output for CSI10 SI10 Input Serial data input to CSI10 SO10 Output Serial data output from CSI10 TI000 Input External count clock input to 16-bit timer/event counter 00 ...
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Port functions: 78K0/KC2-L (1/2) Function Name I/O P00 I/O Port 0. 3-bit I/O port. P01 Input/output can be specified in 1-bit units. Note 1 P02 Use of an on-chip pull-up resistor can be specified by a ...
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Port functions: 78K0/KC2-L (2/2) Function Name I/O P60 I/O Port 6. 4-bit I/O port. Input/output can be specified in 1-bit units. P61 Input of P60 and P61 can be set to SMBus input buffer in P62 1-bit units. P63 ...
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Non-port functions : 78K0/KC2-L (2/4) Function Name I/O ANI8 Input A/D converter analog input ANI9 ANI10 Note 1 AMP0- Operational amplifier 0 input Note 1 AMP0+ Note 1 AMP1- Operational amplifier 1 input Note 1 AMP1+ Note 1 AMP0OUT ...
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Non-port functions : 78K0/KC2-L (3/4) Function Name I/O KR0 to KR3 Input Key interrupt input Note 2 Note 2 KR4 , KR5 Note 2 PCL Output Clock output (for trimming of high-speed system clock, subsystem clock) Real-time counter clock ...
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Non-port functions : 78K0/KC2-L (4/4) Function Name I/O TI50 Input External count clock input to 8-bit timer/event counter 50 TI51 External count clock input to 8-bit timer/event counter 51 TO00 Output 16-bit timer/event counter 00 output TO50 Output 8-bit ...
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Description of Pin Functions Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P00 to P02 (port 0) P00 to P02 function as an I/O port. These ...
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P10 to P17 (port 1) P10 to P17 function as an I/O port. These pins also function as pins for A/D converter analog input, operational amplifier I/O, external interrupt request input, serial interface data I/O, clock I/O, and timer ...
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SO10 This is a serial data output pin of serial interface CSI10. (f) SCK10 This is a serial clock I/O pin of serial interface CSI10. (g) RxD6 This is a serial data input pin of serial interface UART6. (h) ...
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Port mode P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D ...
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TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin from 8-bit timer/event counter 51. (d) TOH1 This is the timer output pin of 8-bit timer H1. ...
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RTCCL This is the real-time counter clock (32 kHz original oscillation) output pin. (c) RTC1HZ This is the real-time counter correction clock (1 Hz division) output pin. (d) INTP6 This is the external interrupt request input pin for which ...
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Control mode P60 to P63 function as serial interface data I/O and clock I/O. (a) SDAA0 This is a serial data I/O pin for serial interface IICA. (b) SCLA0 This is a serial clock I/O pin for serial interface ...
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Port mode P70 to P75 function as an I/O port. P70 to P75 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified ...
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INTP0 This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) EXLVI This is a potential input pin for external low-voltage ...
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AV REF This is the A/D converter reference voltage input pin and the positive power supply pin of port 2 and A/D converter. When the A/D converter is not used, connect this pin directly to V Note Make the ...
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Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 to 2-5 show the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of ...
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Pin Name I/O Circuit Type P00/TI000/INTP0 5-AQ P01/TO00/TI010 Note 1 ANI0/P20/AMP0- 11-P Note 1 ANI1/P21/AMP0OUT / 11-O Note 1 PGAIN Note 1 ANI2/P22/AMP0+ 11-N ANI3/P23 11-G ANI4/P24 ANI5/P25 P30/TOH1/TI51/INTP1 5-AQ P31/INTP2/TOOLC1 P32/TOH1/INTP3/TOOLD1 <R> P60/SCLA0/TxD6 5-AS <R> P61/SDAA0/RxD6 Note 2 37-A ...
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Pin Name P00/TI000 P01/TO00/TI010 Note 1 P10/ANI8/ANP1- /SCK10 Note 1 P11/ANI9/ANP1OUT /SI10 Note 1 P12/ANI10/ANP1+ /SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 Note 1 ANI0/P20/AMP0- Note 1 ANI1/P21/AMP0OUT / Note 1 PGAIN Note 1 ANI2/P22/AMP0+ ANI3/P23 P30/INTP1 P31/INTP2/TOOLC1 P32/INTP3/TOOLD1 P33/TI51/TO51/INTP4 ...
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Pin Name I/O Circuit Type P00/TI000 5-AQ P01/TO00/TI010 Note 1 Note 1 P02 /INTP7 Note 2 P10/ANI8/ANP1- /SCK10 11-L Note 2 P11/ANI9/ANP1OUT /SI10 11-M Note 2 P12/ANI10/ANP1+ /SO10 11-K P13/TxD6 5-AG P14/RxD6 5-AQ P15/TOH0 5-AG P16/TOH1/INTP5 5-AQ P17/TI50/TO50 Note ...
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Table 2-5. Pin I/O Circuit Types (78K0/KC2-L) (2/2) Pin Name I/O Circuit Type P60/SCLA0/SCK11/INTP11 5-AS P61/SDAA0/SI11/INTP10 P62/SO11/INTP9 5-AR P63/INTP8 P70/KR0 5-AQ P71/KR1 P72/KR2 P73/KR3 Note 1 Note 1 P74 /KR4 Note 1 Note 1 P75 /KR5 P120/EXLVI/INTP0 (/SO11) Note 2 ...
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Type 5-AG pullup enable V DD data P-ch output N-ch disable V SS input enable Type 5-AQ pullup enable V DD data P-ch output N-ch disable V SS input enable 62 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit ...
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Type 11-G AV data output disable AV P-ch Comparator + _ N-ch Series resistor string voltage AV SS input enable Type 11-K pullup enable V data output disable AV P-ch Comparator + _ N-ch V REF (Threshold voltage ...
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Type 11-N data output disable P-ch Comparator + _ N-ch V REF (Threshold voltage input enable Type 11-O data output disable P-ch Comparator + _ N-ch V REF (Threshold voltage input enable _ PGA + + ...
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CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (4/4) Type pullup P-ch enable input enable reset reset mask Preliminary User’s Manual U19111EJ2V1UD IN 65 ...
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Memory Space Products in the 78K0/Kx2-L microcontrollers can access memory space. Figures 3-1 to 3-4 show the memory maps. Caution Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding ...
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Figure 3-1. Memory Map ( PD78F0550, 78F0555, 78F0560, 78F0565) FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 384 8 bits FD80H FD7FH Data memory space Reserved 1000H 0FFFH ...
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Figure 3-2. Memory Map ( PD78F0551, 78F0556, 78F0561, 78F0566, 78F0571, 78F0576, 78F0581, 78F0586) FFFFH Special function registers (SFR) 256 FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 512 FD00H FCFFH Data memory space Reserved 2000H 1FFFH ...
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Figure 3-3. Memory Map ( PD78F0552, 78F0557, 78F0562, 78F0567, 78F0572, 78F0577, 78F0582, 78F0587) FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers FEE0H 32 8 bits FEDFH Internal high-speed RAM 768 8 bits FC00H FBFFH Data memory ...
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Figure 3-4. Memory Map ( PD78F0573, 78F0578, 78F0583, 78F0588) FFFFH Special function registers (SFR) 256 FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 FB00H FAFFH Data memory space Reserved 8000H 7FFFH Program Flash memory memory ...
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Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to ...
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The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each ...
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CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be ...
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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing ( PD78F0551, 78F0556, 78F0561, 78F0566, 78F0571, 78F0576, 78F0581, 78F0586) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers FEE0H 32 8 bits FEDFH ...
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Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0552, 78F0557, 78F0562, 78F0567, 78F0572, 78F0577, 78F0582, 78F0587 Special function registers (SFR) 256 x 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0573, 78F0578, 78F0583, 78F0588 Special function registers (SFR) 256 8 bits ...
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Processor Registers The 78K0/Kx2-L microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...
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Auxiliary carry flag (AC) If the operation result has a carry from bit borrow at bit 3, this flag is set (1 reset (0) in all other cases. (e) In-service priority flag (ISP) This ...
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Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H (b) CALL, CALLF, CALLT instructions (when SP = FEE0H (c) Interrupt, BRK instructions (when SP = FEE0H ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit ...
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Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF06H Port register 6 FF07H Port register 7 <R> FF08H 10-bit A/D 8-bit A/D ...
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Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF30H Pull-up resistor option register 0 FF31H Pull-up resistor option register 1 FF33H Pull-up resistor option register 3 FF34H Pull-up resistor option register 4 FF36H Pull-up resistor ...
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Address Special Function Register (SFR) Name FF7AH Serial I/O shift register 11 FF7CH Transmit buffer register 11 <R> FF80H Serial operation mode register 10 <R> FF81H Serial clock selection register 10 <R> FF84H Transmit buffer register 10 FF88H Serial operation ...
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Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name FFB7H Month count register FFB8H Year count register FFB9H Watch error correction register FFBAH 16-bit timer mode control register 00 FFBBH Prescaler mode register 00 FFBCH Capture/compare ...
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Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. [Operand format] [Description example] MOV ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply AV REF V DD Note 78K0/KY2-L: P20 to P23 78K0/KA2-L: P20 to P25 78K0/KB2-L: P20 to P23 ...
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Function Name I/O P00 I/O P01 P20 I/O P21 P22 P23 P30 I/O <R> P60 I/O <R> P61 P121 Input P122 P125 Note PD78F0555, 78F0556, and 78F0557 (products with operational amplifier) only CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions ...
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Function Name I/O P00 I/O Port 0. 2-bit I/O port. P01 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. 6-bit I/O port. P21 Input/output ...
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Function Name I/O P00 I/O P01 P10 I/O P11 P12 P13 P14 P15 P16 P17 P20 I/O P21 P22 P23 P30 I/O P31 P32 P33 P60 I/O P61 P120 I/O P121 Input P122 P125 Note PD78F0576, 78F0577, and 78F0578 ...
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Function Name I/O P00 I/O Port 0. 3-bit I/O port. P01 Input/output can be specified in 1-bit units. Note 1 P02 Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O Port 1. 8-bit ...
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Table 4-5. Port Functions (78K0/KC2-L) (2/2) Function Name I/O P60 I/O Port 6. 4-bit I/O port. Input/output can be specified in 1-bit units. P61 Input of P60 and P61 can be set to SMBus input buffer in P62 1-bit units. ...
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Port Configuration Ports include the following hardware. Item Control registers 78K0/KY2-L, 78K0/KA2-L Port mode register (PMxx): Port register (Pxx): Pull-up resistor option register (PUxx): PU0, PU3, PU6, PU12 Port input mode register 6 (PIM6) Port output mode register 6 ...
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Port 0 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins 20 Pins P00/TI000/INTP0 P00/TI000/INTP0 P01/TO00/TI010 P01/TO00/TI010 Port I/O port with an output latch. Port 0 can be set to the input mode or output mode in ...
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WR PU PU0 PU01 Alternate function RD WR PORT P0 Output latch (P01 PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR : Write ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 WR PU PU0 PU02 RD Alternate function WR PORT P0 Output latch (P02 PM0 PM02 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode ...
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Port 1 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins <R> <R> <R> Note Products with operational amplifier only Port I/O port with an output latch. Port 1 can be set to the input mode or ...
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Table 4-8. Setting Functions of P11/ANI9/AMP1OUT Pin ADPC1 Register PM1 Register Digital I/O Input mode selection Output mode Analog input Input mode selection Output mode Remark ADPC1: A/D port configuration register 1 PM1: Port mode register 1 OPAMP1E: Bit 7 ...
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Products without operational amplifier of 78K0/KB2-L and 78K0/KC2 PU1 PU10 Alternate function RD WR PORT P1 Output latch (P10 PM1 PM10 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: ...
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Products with operational amplifier of 78K0/KB2-L and 78K0/KC2 PORT WR PM P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : Write signal CHAPTER ...
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Products without operational amplifier of 78K0/KB2-L and 78K0/KC2 PU1 PU11 Alternate function RD WR PORT Output latch (P11 PM1 PM11 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register ...
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Products with operational amplifier of 78K0/KB2-L and 78K0/KC2 PORT WR PM P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : Write signal CHAPTER ...
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Products without operational amplifier of 78K0/KB2-L and 78K0/KC2 PU1 PU12 RD WR PORT P1 Output latch (P12 PM1 PM12 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode ...
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Products with operational amplifier of 78K0/KB2-L and 78K0/KC2 PORT WR PM P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : Write signal CHAPTER ...
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WR PU PU1 PU13 RD WR PORT P1 Output latch (P13 PM1 PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : Write signal 118 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P14 WR PU PU1 PU14 Alternate function RD WR PORT P1 Output latch (P14 PM1 PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode ...
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WR PU PU1 PU15 RD WR PORT P1 Output latch (P15 PM1 PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : Write signal 120 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT P1 Output latch (P16, P17 PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up ...
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Port 2 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins Note P20/ANI0/AMP0- P20/ANI0/AMP0- Note P21/ANI1/AMP0OUT / P21/ANI1/AMP0OUT Note Note PGAIN PGAIN Note P22/ANI2/AMP0+ P22/ANI2/AMP0+ P23/ANI3 P23/ANI3 P24/ANI4 P25/ANI5 Note Products with operational amplifier only Port I/O ...
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Table 4-10. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin ADPC0 PM2 Register OPAMP0E bit Register Digital I/O Input mode 0 selection 1 Output mode 0 1 Analog input Input mode 0 selection 0 1 Output mode Table 4-11. Setting Functions of P23/ANI3 ...
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Products without operational amplifier RD WR PORT Output latch (P20 PM2 PM20 (2) Products with operational amplifier RD WR PORT P2 Output latch (P20 PM2 PM20 Operational amplifier (-) input P2: Port register 2 PM2: ...
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Products without operational amplifier RD WR PORT Output latch (P21 PM2 PM21 (2) Products with operational amplifier RD WR PORT P2 Output latch (P21 PM2 PM21 Operational amplifier output P2: Port register 2 PM2: Port ...
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Products without operational amplifier RD WR PORT Output latch (P22 PM2 PM22 (2) Products with operational amplifier RD WR PORT P2 Output latch (P22 PM2 PM22 Operational amplifier (+) input P2: Port register 2 PM2: ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P23-P27 RD WR PORT P2 Output latch (P23 to P27 PM2 PM23 to PM27 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR ...
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Port 3 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins 20 Pins P30/TOH1/TI51/INTP1 P30/TOH1/TI51/INTP1 P31/INTP2/TOOLC1 P32/INTP3/TOOLD1 Port I/O port with an output latch. Port 3 can be set to the input mode or output mode in ...
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WR PU PU3 PU30 Alternate function RD WR PORT P3 Output latch (P30 PM3 PM30 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read ...
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WR PU PU3 PU30 Alternate function RD WR PORT P3 Output latch (P30 PM3 PM30 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P31 WR PU PU3 PU31 Alternate function RD WR PORT P3 Output latch (P31 PM3 PM31 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode ...
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WR PU PU3 PU32 Alternate function RD WR PORT P3 Output latch (P32 PM3 PM32 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR : Write signal 132 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P33 WR PU PU3 PU33 Alternate function RD WR PORT P3 Output latch (P33 PM3 PM33 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: ...
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Port 4 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins 20 Pins Remark Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL). Port I/O port with an output ...
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WR PU PU4 PU40 Alternate function RD WR PORT P4 Output latch (P40) Alternate function (RTC) Alternate function (CSI11 PM4 PM40 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 MUXSEL: ...
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WR PU PU4 PU41 Alternate function RD WR PORT P4 Output latch (P41 PM4 PM41 Alternate function <R> PORT Output latch WR PM P4: Port register 4 PU4: Pull-up resistor option register 4 ...
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Port 6 78K0/KY2-L ( PD78F055x) 16 Pins <R> P60/SCLA0/TxD6 <R> P61/SDAA0/RxD6 Port I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode ...
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WR PU PU6 PU60 Alternate function RD WR PORT P6 Output latch (P60 PM6 PM60 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PIM6: Port input mode register 6 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P61 WR PU PU6 PU61 Alternate function RD WR PORT P6 Output latch (P61 PM6 PM61 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: ...
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WR PU PU6 PU62 Alternate function RD WR PORT P6 Output latch (P62 PM6 PM62 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 POM6: Port output mode register 6 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P63 WR PU PU6 PU63 Alternate function RD WR PORT P6 Output latch (P63 PM6 PM63 P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode ...
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Port 7 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins 20 Pins Port I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port ...
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Port 12 78K0/KY2-L 78K0/KA2-L ( PD78F055x) ( PD78F056x) 16 Pins 20 Pins P121/X1/TOOLC0 P121/X1/TOOLC0 P122/X2/EXCLK/ P122/X2/EXCLK/ TOOLD0 TOOLD0 P125/RESET P125/RESET Remark Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL). P120 ...
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WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120 PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WR : Write ...
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WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120) Alternate function WR PM PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 MUXSEL: Port alternate ...
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Figure 4-28. Block Diagram of P121 to P124 RD RD OSCCTL: Clock operation mode select register RD: Read signal WR : Write signal 146 CHAPTER 4 PORT FUNCTIONS OSCCTL OSCSEL/ OSCSELS OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS Preliminary User’s Manual U19111EJ2V1UD ...
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Figure 4-29. Block Diagram of P125 WR PU PU12 PU125 RD Internal reset WR PM RSTMASK RSTM PU12: Pull-up resistor option register 12 RD: Read signal WR : Write signal RSTMASK: Reset pin mode register Remark After reset, the external ...
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Registers Controlling Port Function Port functions are controlled by the following eight types of registers. Port mode registers (PMxx) Port registers (Pxx) Pull-up resistor option registers (PUxx) Port input mode register 6 (PIM6) Port output mode register 6 (POM6) ...
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Figure 4-31. Format of Port Mode Register (78K0/KA2-L) Symbol PM0 Note PM2 1 1 PM25 PM3 PM6 PMmn 0 Output mode (output buffer on) 1 Input mode (output ...
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Figure 4-33. Format of Port Mode Register (78K0/KC2-L) Symbol PM0 PM1 PM17 PM16 PM15 Note 2 Note 2 Note 2 PM2 PM27 PM26 PM25 PM3 PM4 ...
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Figure 4-34. Format of Port Register (78K0/KY2-L) Symbol P12 0 0 P125 Pmn Output data control (in output mode) 0 Output ...
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Figure 4-36. Format of Port Register (78K0/KB2-L) Symbol P17 P16 P15 P12 0 0 P125 Pmn Output data control (in ...
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Figure 4-37. Format of Port Register (78K0/KC2-L) Symbol P17 P16 P15 Note 2 Note 2 Note 2 P2 P27 P26 P25 ...
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Figure 4-38. Format of Pull-up Resistor Option Register (78K0/KY2-L) Symbol PU0 PU3 PU6 PU12 0 0 PU125 PUmn 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor ...
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Figure 4-40. Format of Pull-up Resistor Option Register (78K0/KB2-L) Symbol PU0 PU1 PU17 PU16 PU15 PU3 PU6 PU12 0 0 PU125 PUmn 0 On-chip pull-up resistor not connected ...
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Port input mode register 6 (PIM6) This register sets the input buffer of P60 or P61 in 1-bit units. When using an input compliant with the SMBus 2 Specifications communication, select the SMBus input buffer. This ...
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Reset pin mode register (RSTMASK) This register sets the pin function of RESET/P125 (external reset input/input-dedicated port). This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: ...
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Figure 4-45. Format of A/D Port Configuration Register 0 (ADPC0) (1) 78K0/KY2-L Address: FF2EH After reset: 00H Symbol 7 ADPC0 0 (2) 78K0/KA2-L Address: FF2EH After reset: 00H Symbol 7 ADPC0 0 (3) 78K0/KB2-L Address: FF2EH After reset: 00H ...
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Figure 4-46. Format of A/D Port Configuration Register 1 (ADPC1) Address: FF2FH After reset: 07H Symbol 7 ADPC1 0 ADPCSn 0 1 Cautions 1. Set the pin set to analog input to the input mode by using port mode ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...
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Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Tables 4-12 to 4-15. Table 4-12. Settings ...
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Table 4-12. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Note 1 P121 X1 TOOLC0 Note 1 P122 X2 Note 1 EXCLK TOOLD0 <R> Note 2 P125 RESET Notes 1. When using the P121 ...
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Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P00 TI000 INTP0 P01 TI010 TO00 Note 1 P20 ANI0 Notes 1, 2 AMP0- Note 1 P21 ANI1 AMP0OUT Notes 1, 2 PGAIN Note ...
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Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Note 1 P121 X1 TOOLC0 Note 1 P122 X2 Note 1 EXCLK TOOLD0 <R> Note 2 P125 RESET Notes 1. When using the P121 ...
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Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P00 TI000 P01 TI010 TO00 Note 2 P10 ANI8 Notes 1, 2 AMP1- SCK10 Note 2 P11 ANI9 AMP1OUT SI10 Note 2 P12 ...
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Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P30 INTP1 P31 INTP2 TOOLC1 P32 INTP3 TOOLD1 P33 INTP4 TI51 TO51 Notes 1, 2 P60 SCLA0 INTP11 Notes 1, 2 P61 SDAA0 INTP10 ...
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Table 4-15. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P00 TI000 P01 TI010 TO00 Note 1 Note 1 P02 INTP7 Note 3 P10 ANI8 Notes 2, 3 AMP1- SCK10 Note 3 P11 ...
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Table 4-15. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P30 INTP1 P31 INTP2 TOOLC1 P32 INTP3 TOOLD1 P33 INTP4 TI51 TO51 P40 RTCCL RTCDIV (SCK11) P41 RTC1HZ (SI11) Note 1 Note 1 P42 ...
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Table 4-15. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P70 to P73, KR0 to KR3, KR4 Note 1 P74 , Note 1 P75 P120 INTP0 EXLVI (SO11) Note 2 P121 X1 TOOLC0 Note ...
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Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This ...
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Internal low-speed oscillation clock (clock for watchdog timer) Internal low-speed oscillator This circuit oscillates a clock of f clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can ...
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Figure 5-1. Block Diagram of Clock Generator (78K0/KY2-L, 78K0/KA2-L, 78K0/KB2-L) Clock operation mode Main OSC select register control register (OSCCTL) (MOC) EXCLK OSCSEL MSTOP High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK External input /P122 Internal ...
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Clock operation mode Main OSC select register control register (OSCCTL) (MOC) EXCLK OSCSEL High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK External input Internal high- /P122 f EXCLK clock speed oscillator (4 MHz (TYP.)/ 8 ...
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Remark clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK f : High-speed system clock frequency Main system clock frequency ...
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Figure 5-3. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH After reset: 00H Symbol <7> OSCCTL EXCLK OSCSEL EXCLK OSCSEL Cautions 1. To change the value of EXCLK and OSCSEL, be sure to confirm ...
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Caution <R> (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...
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Figure 5-6. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 01H Symbol 7 6 PCC 0 XTSTART CLS 0 Main system clock 1 Subsystem clock CSS PCC2 ...
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Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (f ) CPU High-Speed System Note 1 Clock At 10 MHz Operation ...
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Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 5-7. Format of Internal ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ...
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Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for ...
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Peripheral enable register 0 (PER0) This register controls the supply of the real-time counter control clock. The power consumption can be reduced by stopping the real-time counter control clock supply. PER0 can be set by a 1-bit or 8-bit ...
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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input ...
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Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-13 and 5-14 to avoid an adverse effect from wiring capacitance. • Keep the wiring length ...
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Figure 5-15. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (c) Wiring near high alternating current Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, ...
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Figure 5-15. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (refer to Figure 5-1 and 5-2). Main system clock f XP High-speed system clock ...
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Figure 5-16. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0)) Power supply 1.8 V voltage ( 1.61 V (TYP.) 0.5 V/ms (MIN.) 0 ...
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Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 ...
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Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. 2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation ...
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Example of setting procedure when oscillating the X1 clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is ...
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Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of ...
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To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the ...
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Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> Restarting oscillation of the internal high-speed oscillation clock (Refer to 5.6.2 (1) ...
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Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. Executing the STOP instruction to set the STOP mode Setting RSTOP to 1 and stopping ...
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Example of controlling subsystem clock The following two types of subsystem clocks XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock ...
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Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillation (Refer to 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using ...