IC MCU 8BIT FLASH 38-TSSOP

 

SAK-XC866L-1FRA AB

Manufacturer Part NumberSAK-XC866L-1FRA AB
DescriptionIC MCU 8BIT FLASH 38-TSSOP
ManufacturerInfineon Technologies
SeriesXC8xx
SAK-XC866L-1FRA AB datasheets

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Specifications of SAK-XC866L-1FRA AB

Core ProcessorXC800Core Size8-Bit
Speed86MHzConnectivityLIN, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o19
Program Memory Size4KB (4K x 8)Program Memory TypeFLASH
Ram Size768 x 8Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case38-TSSOP
Data Bus Width8 bitData Ram Size750 B
Interface TypeUART, SSCMaximum Clock Frequency26.67 MHz
Number Of Programmable I/os27Number Of Timers3
Operating Supply Voltage3.3 V, 5 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Other namesSP000235421
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3.11.1
Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock f
FDM
FDEN
f
f
PCLK
DIV
Prescaler
clk
Figure 29
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
MOD
output of the prescaler (f
DIV
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See
The baud rate (f
) value is dependent on the following parameters:
BR
• Input clock f
PCLK
BRPRE
• Prescaling factor (2
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
Data Sheet
, see
Figure
29.
PCLK
Fractional Divider
FDSTEP
1
FDEN&FDM
1
0
Adder
f
00
DIV
01
0
11
f
FDRES
(overflow)
MOD
10
11
10
01
‘0’
00
) if the fractional divider is disabled (FDEN = 0). For baud rate
) defined by bit field BRPRE in register BCON
68
XC866
Functional Description
8-Bit Reload Value
f
0
BR
1
8-Bit Baud Rate Timer
R
NDOV
Section
3.12.
V1.2, 2007-10