SAK-XC888C-6FFI 5V AC Infineon Technologies, SAK-XC888C-6FFI 5V AC Datasheet
SAK-XC888C-6FFI 5V AC
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XC886/888CLM 8-Bit Single Chip Microcontroller Data Sheet V1.2 2009- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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XC886/888CLM 8-Bit Single Chip Microcontroller Data Sheet V1.2 2009- ...
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XC886/888 Data Sheet Revision History: V1.2 2009-07 Previous Versions: V1.0, V1.1 Page Subjects (major changes since last revision) Changes from V1.1 2009-01 to V1.2 2009-07 89 Note on LIN baud rate detection is added. 92 RXD slave line in SSC ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 68 3.7 Reset Control . . . . . . . . . . . . . . . . ...
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Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.4 On-Chip Oscillator Characteristics ...
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Single Chip Microcontroller 1 Summary of Features The XC886/888 has the following features: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data ...
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... On-chip debug support – 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) – 64 bytes of monitor RAM • Packages: – PG-TQFP-48 – PG-TQFP-64 T • Temperature range A – SAF (- °C) – SAK (-40 to 125 °C) Data Sheet : 2 XC886/888CLM Summary of Features V1.2, 2009-07 ...
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... Industrial), as shown in Table 2 Device Profile Sales Type SAK-XC886*/888*-8FFA 5V SAK-XC886*/888*-6FFA 5V SAF-XC886*/888*-8FFA 5V SAF-XC886*/888*-6FFA 5V SAF-XC886*/888*-8FFI 5V SAF-XC886*/888*-6FFI 5V Data Sheet CAN ...
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... Table 2 Device Profile (cont’d) Sales Type SAK-XC886*/888*-8FFA 3V3 Flash SAK-XC886*/888*-6FFA 3V3 Flash SAF-XC886*/888*-8FFA 3V3 Flash SAF-XC886*/888*-6FFA 3V3 Flash SAF-XC886*/888*-8FFI 3V3 SAF-XC886*/888*-6FFI 3V3 Note: The asterisk (*) above denotes the device configuration letters from Corresponding ROM derivatives will be available on request ...
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General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC886/888. 2.1 Block Diagram The block diagram of the XC886/888 is shown in XC886/888 12-Kbyte 1) Boot ROM 256-byte RAM + 64-byte monitor ...
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Logic Symbol The logic symbols of the XC886/888 are shown DDP SSP V AREF V AGND RESET XC886 MBC TMS XTAL1 XTAL2 V V DDC SSC Figure 3 XC886/888 Logic Symbol Data Sheet General Device Information ...
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Pin Configuration The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is shown in Figure 4, while that of the XC888, which is based on the PG-TQFP-64 package, is shown in Figure ...
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P3.2 49 P3.3 50 P3.4 51 P3.5 52 RESET SSP V 55 DDP MBC 58 P4.0 59 ...
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Pin Definitions and Functions The functions and default states of the XC886/888 external pins are provided in Table 3 Pin Definitions and Functions Symbol Pin Number (TQFP-48/64) P0 P0.0 11/17 P0.1 13/21 P0.2 12/18 P0.3 48/63 Data Sheet Type ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P0.4 1/64 P0.5 2/1 P0.6 –/2 P0.7 47/62 Data Sheet Type Reset Function State Hi-Z MTSR_1 CC62_1 TXD1_0 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 PU GPIO PU CLKOUT_1 Clock ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P1 P1.0 26/34 P1.1 27/35 P1.2 28/36 P1.3 29/37 P1.4 30/38 P1.5 31/39 Data Sheet Type Reset Function State I/O Port 1 Port 8-bit bidirectional general ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P1.6 8/10 P1.7 9/11 Data Sheet Type Reset Function State PU CCPOS1_1 T12HR_0 EXINT6_0 RXDC0_2 T21_1 PU CCPOS2_1 T13HR_0 T2_1 TXDC0_2 P1.5 and P1.6 can be used as a ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P2 P2.0 14/22 P2.1 15/23 P2.2 16/24 P2.3 19/27 P2.4 20/28 P2.5 21/29 P2.6 22/30 P2.7 25/33 Data Sheet Type Reset Function State I Port 2 Port 2 is ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P3 P3.0 35/43 P3.1 36/44 P3.2 37/49 P3.3 38/50 P3.4 39/51 P3.5 40/52 P3.6 33/41 Data Sheet Type Reset Function State I/O Port 3 Port 8-bit ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P3.7 34/42 Data Sheet Type Reset Function State Hi-Z EXINT4 COUT63_0 15 XC886/888CLM General Device Information External Interrupt Input 4 Output of Capture/Compare channel 3 V1.2, 2009-07 ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P4 P4.0 45/59 P4.1 46/60 P4.2 –/61 P4.3 32/40 P4.4 –/45 P4.5 –/46 P4.6 –/47 P4.7 –/48 Data Sheet Type Reset Function State I/O Port 4 Port 4 is ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) P5 P5.0 –/8 P5.1 –/9 P5.2 –/12 P5.3 –/13 P5.4 –/14 P5.5 –/15 P5.6 –/19 P5.7 –/20 Data Sheet Type Reset Function State I/O Port 5 Port 5 is ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64 17, 43/ DDP 7, 25 18, 42/26, 54 – SSP V 6/6 DDC V 5/5 SSC V 24/32 AREF V 23/31 AGND XTAL1 4/4 XTAL2 ...
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Functional Description Chapter 3 provides an overview of the XC886/888 functional description. 3.1 Processor Architecture The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 ...
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Memory Organization The XC886/888 CPU operates in the following five address spaces: • 12 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 1.5 Kbytes of XRAM memory (XRAM can be read/written as ...
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Therefore, even though the ROM device contains either a 24-Kbyte or 32- Kbyte ROM, the maximum size of code that can be placed in the ROM is the given size less four bytes. 3.2.1 Memory Protection Strategy ...
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Table 4 Flash Protection Modes (cont’d) Flash Protection Without hardware protection P-Flash program Possible and erase D-Flash Read instructions in contents can be any program memory read by External access Not possible to D-Flash D-Flash Possible program D-Flash erase Possible ...
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Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range All registers, except the program counter, reside in the SFR area. The H H SFRs include pointers and ...
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SFR Data (to/from CPU) Figure 8 Address Extension by Mapping Data Sheet Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw Module n SFRs Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module ...
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SYSCON0 System Control Register Field Bits RMAP [7:5], 3,1 Note: The RMAP bit should be cleared/set by ANL or ORL instructions. 3.2.2.2 Address Extension by Paging Address extension is further performed ...
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SFR Address (from CPU) SFR Data (to/from CPU) Figure 9 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming ...
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Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt ...
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The page register has the following definition: MOD_PAGE Page Register for module MOD Field Bits PAGE [2:0] STNR [5:4] Data Sheet STNR Type Description rw Page Bits When written, the ...
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Field Bits OP [7: 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access ...
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Password Register PASSWD Password Register 7 6 PASS Field Bits MODE [1:0] PROTECT_S 2 PASS [7:3] Data Sheet Type Description rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected ...
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XC886/888 Register Overview The SFRs of the XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU ...
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Table 5 CPU Register Overview (cont’d) Addr Register Name A8 H IEN0 Reset Interrupt Enable Register Reset Interrupt Priority Register B9 H IPH Reset Interrupt Priority High Register D0 H ...
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Table 6 MDU Register Overview (cont’d) Addr Register Name B3 H MR1 Reset MDU Result Register MD2 Reset MDU Operand Register MR2 Reset MDU Result Register 2 B5 ...
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Table 7 CORDIC Register Overview (cont’d) Addr Register Name A0 H CD_STATC Reset CORDIC Status and Data Control Register A1 H CD_CON Reset CORDIC Control Register 3.2.4.4 System Control Registers The system control SFRs can be ...
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Table 8 SCU Register Overview (cont’d) Addr Register Name BC H NMISR Reset NMI Status Register BD H BCON Reset Baud Rate Control Register Reset Baud Rate Timer/Reload Register E9 H ...
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Table 8 SCU Register Overview (cont’d) Addr Register Name BE H COCON Reset Clock Output Control Register E9 H MISC_CON Reset Miscellaneous Control Register RMAP = 0, PAGE XADDRH Reset On-chip ...
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Table 9 WDT Register Overview (cont’d) Addr Register Name BE H WDTL Reset Watchdog Timer Register Low BF H WDTH Reset Watchdog Timer Register High 3.2.4.6 Port Registers The Port SFRs can be accessed in the ...
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Table 10 Port Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE P0_PUDSEL Reset Pull-Up/Pull-Down Select Register 86 H P0_PUDEN Reset Pull-Up/Pull-Down Enable Register 90 H P1_PUDSEL Reset ...
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Table 10 Port Register Overview (cont’d) Addr Register Name 93 H P5_ALTSEL1 Reset Alternate Select 1 Register B0 H P3_ALTSEL0 Reset Alternate Select 0 Register B1 H P3_ALTSEL1 Reset Alternate Select ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CD H ADC_LCBR Reset Limit Check Boundary Register CE H ADC_INPCR0 Reset Input Class 0 Register CF H ADC_ETRCR Reset External Trigger Control Register RMAP ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name D3 H ADC_RESR3H Reset Result Register 3 High RMAP = 0, PAGE ADC_RESRA0L Reset Result Register 0, View A Low CB H ADC_RESRA0H Reset: ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CC H ADC_CHINSR Reset Channel Interrupt Set Register CD H ADC_CHINPR Reset Channel Interrupt Node Pointer Register CE H ADC_EVINFR Reset Event Interrupt Flag Register ...
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Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 T2 Register Overview Addr Register Name RMAP = T2_T2CON Reset Timer 2 Control Register ...
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Table 13 T21 Register Overview (cont’d) Addr Register Name C5 H T21_T2H Reset Timer 2 Register High 3.2.4.10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FA H CCU6_CC60SRL Reset Capture/Compare Shadow Register for Channel CC60 Low FB H CCU6_CC60SRH Reset Capture/Compare Shadow Register for Channel CC60 High FC H CCU6_CC61SRL Reset: 00 ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FB H CCU6_CC60RH Reset Capture/Compare Register for Channel CC60 High FC H CCU6_CC61RL Reset Capture/Compare Register for Channel CC61 Low FD H CCU6_CC61RH Reset Capture/Compare ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FB H CCU6_TCTR2H Reset Timer Control Register 2 High FC H CCU6_MODCTRL Reset Modulation Control Register Low FD H CCU6_MODCTRH Reset Modulation Control Register High ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FE H CCU6_CMPSTATL Reset Compare State Register Low FF H CCU6_CMPSTATH Reset Compare State Register High 3.2.4.11 UART1 Registers The UART1 SFRs can be accessed in the ...
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SSC Registers The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 16 SSC Register Overview Addr Register Name RMAP = SSC_PISEL Reset Port Input Select Register AA H ...
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Table 17 CAN Register Overview (cont’d) Addr Register Name DB H DATA0 Reset CAN Data Register DATA1 Reset CAN Data Register DATA2 Reset CAN Data Register 2 DE ...
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Table 18 OCDS Register Overview (cont’d) Addr Register Name EC H MMWR2 Reset Monitor Work Register 2 Data Sheet Bit Bit Field Type 51 XC886/888CLM Functional Description MMWR2 rw V1.2, 2009-07 ...
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Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not ...
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Table 19 shows the Flash data retention and endurance targets. Table 19 Flash Data Retention and Endurance (Operating Conditions apply) Retention Endurance Program Flash 20 years 1,000 cycles 20 years 1,000 cycles Data Flash 20 years 1,000 cycles 5 years ...
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Sector 2: 128-byte Sector 1: 128-byte Sector 0: 3.75-Kbyte P-Flash Figure 11 Flash Bank Sectorization The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and ...
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Flash Programming Width For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must ...
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Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC886/888 interrupt system provides extended ...
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Timer 0 Overflow Timer 1 Overflow UART Receive UART Transmit EINT0 EXINT0 EXICON0.0/1 EINT1 EXINT1 EXICON0.2/3 Bit-addressable Request flag is cleared by hardware Figure 14 Interrupt Request Sources (Part 1) Data Sheet TF0 TCON.5 ET0 IEN0.1 TF1 TCON.7 ET1 IEN0.3 ...
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Timer 2 Overflow T2_T2CON.7 T2EX T2_T2CON.6 EXEN2 T2_T2CON.3 EDGES Normal Divider EL Overflow T2_T2MOD.5 End of EOFSYN Synch Byte FDCON.4 Synch Byte ERRSYN Error FDCON.5 MultiCAN_0 ADC_0 ADC_1 MultiCAN_1 MultiCAN_2 Bit-addressable Request flag is cleared by hardware Figure 15 Interrupt ...
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SSC_EIR SSC_TIR SSC_RIR EINT2 EXINT2 EXICON0.4/5 UART1_SCON.0 UART1 UART1_SCON.1 Timer 21 Overflow T21_T2CON.7 T21EX EXF2 T21_T2CON.6 EXEN2 T21_T2CON.3 EDGES Normal Divider EL Overflow T21_T2MOD.5 Cordic MDU_0 MDU_1 Bit-addressable Request flag is cleared by hardware Figure 16 Interrupt Request Sources (Part ...
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EINT3 EXINT3 EXICON0.6/7 EINT4 EXINT3 EXICON1.0/1 EINT5 EXINT5 EXICON1.2/3 EINT6 EXINT6 EXICON1.4/5 MultiCAN_3 CANSRC3 IRCON2.4 Bit-addressable Request flag is cleared by hardware Figure 17 Interrupt Request Sources (Part 4) Data Sheet EXINT3 IRCON0.3 EXINT4 IRCON0.4 >=1 EXINT5 004B EXM IRCON0.5 ...
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CCU6 interrupt node 0 CCU6SR0 IRCON3.0 MultiCAN_4 CANSRC4 IRCON3.1 CCU6 interrupt node 1 CCU6SR1 IRCON3.4 MultiCAN_5 CANSRC5 IRCON3.5 CCU6 interrupt node 2 CCU6SR2 IRCON4.0 MutliCAN_6 CANSRC6 IRCON4.1 CCU6 interrupt node 3 CCU6SRC3 IRCON4.4 MultiCAN_7 CANSRC7 IRCON4.5 Bit-addressable Request flag is ...
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Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source ...
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Table 20 Interrupt Vector Addresses (cont’d) Interrupt Vector Source Address XINTR6 0033 H XINTR7 003B H XINTR8 0043 H XINTR9 004B H XINTR10 0053 H XINTR11 005B H XINTR12 0063 H XINTR13 006B H Data Sheet Assignment for XC886/888 MultiCAN ...
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Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by ...
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Parallel Ports The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4), while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 5 (P5). ...
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Figure 19 shows the structure of a bidirectional port pin. Px_PUDSEL Internal Bus Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 AltDataOut 3 ...
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Figure 20 shows the structure of an input-only port pin. Internal Bus AltDataIn AnalogIn Figure 20 General Structure of Input Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register enable In Px_DATA Data Register Schmitt ...
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Power Supply System with Embedded Voltage Regulator The XC886/888 microcontroller requires two different levels of power supply: • 3 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip ...
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Reset Control The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC886/888 is first powered up, the status of certain pins (see be defined to ensure ...
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Voltage 5V 2.5V 2.3V 0.9*V DDC Voltage 5V < 0.4V 0V typ. < 50 µ Figure 23 DDP, DDC The second type of reset in XC886/888 is the hardware reset. This reset function can be used during normal ...
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Module Reset Behavior Table 22 lists the functions of the XC886/888 and the various reset types that affect these functions. The symbol “ ” signifies that the particular function is reset to its default state. Table 22 Effect of ...
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BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero. 2) OSC is bypassed in MultiCAN BSL mode 3) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. ...
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OSC P:1 fosc OSCDISC Figure 24 CGU Block Diagram PLL Base Mode When the oscillator is disconnected from the PLL, the system clock is derived from the VCO base (free running) frequency clock Prescaler Mode (VCO Bypass Operation) In VCO ...
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PLL Mode The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode ...
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Table 25 shows the VCO range for the XC886/888. Table 25 VCO Range f f VCOmin VCOmax 150 200 100 150 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external ...
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XTAL1 MHz XC886/888 Oscillator XTAL2 Fundamental Mode Crystal Crystal Frequency MHz MHz MHz MHz 12 ...
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Clock Management The CGU generates all clock signals required within the microcontroller from a single f clock, . During normal system operation, the typical frequencies of the different sys modules are as follow: • CPU clock: CCLK, SCLK = ...
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For power saving purposes, the clocks may be disabled or slowed down according to Table 26. Table 26 System frequency ( Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the ...
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Power Saving Modes The power saving modes of the XC886/888 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some ...
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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must ...
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If the WDT is not serviced before the timer overflow, a system malfunction is assumed result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST). The ...
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FFFF H WDTWINB WDTREL Figure 29 WDT Timing Diagram Table 27 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 27 Watchdog Time Ranges Reload ...
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Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC886/888 Core in real-time control applications, which require fast mathematical computations. ...
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CORDIC Coprocessor The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions. Features • Modes of operation – Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, ...
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Interrupt enabling and corresponding flag 3.13 UART and UART1 The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a ...
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Figure 30. FDM FDEN f f PCLK DIV Prescaler clk Figure 30 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and ...
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The following formulas calculate the final baud rate without and with the fractional divider respectively: ----------------------------------------------------------------------------------- - where 2 baud rate = × 16 baud rate The maximum baud rate that can be generated is limited to clock of 24 ...
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Table 31 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK (2BRPRE) 24 MHz 1 12 MHz 1 8 MHz 1 6 MHz 1 3.13.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3 ...
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LIN Protocol The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte ...
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The header consists of a break and synch pattern followed by an identifier. Among these three fields, ...
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High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received ...
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PCLK Baud-rate Generator Transmit Buffer Register TB Figure 32 SSC Block Diagram Data Sheet Clock Control Shift Clock RIR TIR SSC Control Block Register CON EIR Status Control Pin 16-Bit Shift Control Register Receive Buffer Register RB Internal Bus 92 ...
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Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 ...
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Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table ...
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Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and ...
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T12 clock control start T13 interrupt control Figure 33 CCU6 Block Diagram Data Sheet module kernel compare channel 0 1 dead- channel 1 time 1 control channel 2 1 channel 3 compare input / output ...
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Controller Area Network (MultiCAN) The MultiCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. ...
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CAN functionality according to CAN specification V2.0 B active. • Dedicated control registers are provided for each CAN node. • A data transfer rate MBaud is supported. • Flexible and powerful message transfer control and error ...
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Analog-to-Digital Converter The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input ...
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GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required ADC PCLK f Figure 35 ADC Clocking Scheme f For module clock = 24 MHz, the analog clock ...
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However important to note that the conversion error could increase due to loss of charges on the capacitors, if 3.21.2 ADC Conversion Sequence The analog-to-digital conversion procedure consists of the following phases: • Synchronization phase ( t • ...
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On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • Use the built-in debug functionality of the XC800 ...
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JTAG Module TMS TCK Debug JTAG TDI Interface TDO MBC Monitor & Bootstrap loader Control line Suspend Control System Control Reset Unit Clock - parts of OCDS Figure 37 OCDS Block Diagram 3.22.1 JTAG ID Register This is a read-only ...
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Chip Identification Number The XC886/888 identity (ID) register is located at Page 1 of address B3 ID register is 09 for Flash devices and 22 H identification of product variants, the Chip Identification Number, which is an unique number ...
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Table 36 Chip Identification Number (cont’d) Product Variant XC886-6FFA 3V3 XC888-6FFA 3V3 XC886CLM-8FFA 5V XC888CLM-8FFA 5V XC886LM-8FFA 5V XC888LM-8FFA 5V XC886CLM-6FFA 5V XC888CLM-6FFA 5V XC886LM-6FFA 5V XC888LM-6FFA 5V XC886CM-8FFA 5V XC888CM-8FFA 5V XC886C-8FFA 5V XC888C-8FFA 5V XC886-8FFA 5V XC888-8FFA 5V ...
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Table 36 Chip Identification Number (cont’d) Product Variant XC886LM-6RFA 3V3 XC888LM-6RFA 3V3 XC886CM-8RFA 3V3 XC888CM-8RFA 3V3 XC886C-8RFA 3V3 XC888C-8RFA 3V3 XC886-8RFA 3V3 XC888-8RFA 3V3 XC886CM-6RFA 3V3 XC888CM-6RFA 3V3 XC886C-6RFA 3V3 XC888C-6RFA 3V3 XC886-6RFA 3V3 XC888-6RFA 3V3 XC886CLM-8RFA 5V XC888CLM-8RFA 5V ...
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Table 36 Chip Identification Number (cont’d) Product Variant XC888CM-6RFA 5V XC886C-6RFA 5V XC888C-6RFA 5V XC886-6RFA 5V XC888-6RFA 5V Data Sheet Chip Identification Number AA-Step AB-Step 22891503 - H 22891542 - H 22891543 - H 22891562 - H 22891563 - H ...
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Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC886/888. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 4.1.1 ...
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Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC886/888 can be subjected to without permanent damage. Table 4-1 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with ...
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... Limit Values min. V 4.5 DDP V 3.0 DDP 2.3 DDC 1) f 88.8 SYS T -40 A -40 110 XC886/888CLM Electrical Parameters Unit Notes/ Conditions max. 5 Device 3.6 V 3.3V Device V 2.7 V 103.2 MHz °C 85 SAF- XC886/888... °C 125 SAK- XC886/888... Please refer to SYS V1.2, 2009-07 Figure 26 ...
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DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 38 provides the characteristics of the input/output pins of the XC886/888. Table 38 Input/Output Characteristics (Operating Conditions apply) Parameter V = ...
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Table 38 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Input high voltage on RESET pin Input high voltage on TMS pin Input Hysteresis on port pins Input Hysteresis on XTAL1 Input low voltage at XTAL1 Input high voltage at XTAL1 ...
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Table 38 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Maximum current out 3.3 V Range DDP Output low voltage Output high voltage Input low voltage on port pins (all except P0.0 & P0.1) Input low ...
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Table 38 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Input high voltage at XTAL1 Pull-up current Pull-down current Input leakage current Input current at XTAL1 Overload current on any pin Absolute sum of overload currents Voltage on any pin V ...
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Supply Threshold Characteristics Table 39 provides the characteristics of the supply threshold in the XC886/888. 5.0V VDDP 2.5V VDDC V DDCPOR Figure 38 Supply Threshold Parameters Table 39 Supply Threshold Parameters (Operating Conditions apply) Parameters 1) V prewarning voltage ...
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ADC Characteristics The values in the table below are given for an analog power supply between 4 5.5 V. The ADC can be used with an analog power supply down But in this case, ...
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Table 40 ADC Characteristics (Operating Conditions apply; Parameter Symbol K Overload current OVD coupling factor for digital I/O pins C Switched AREFSW capacitance at the reference voltage input C Switched AINSW capacitance at the analog voltage inputs R Input resistance ...
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R EXT V C AIN V Figure 39 ADC Input Circuits Data Sheet ANx EXT V AGNDx Reference Voltage Input Circuitry R V AREFx AREF V AGNDx 118 XC886/888CLM Electrical Parameters Analog Input Circuitry R AIN AINSW AREF, ...
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ADC Conversion Timing t t Conversion time ADC r = CTC + 2 for CTC = for CTC = CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control ...
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Power Supply Current Table 41, Table 42, Table 43 supply current in the XC886/888. Table 41 Power Supply Current Parameters (Operating Conditions apply range) DDP Parameter Range DDP Active Mode Idle Mode Active ...
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Table 42 Power Down Current (Operating Conditions apply; Parameter Range DDP Power-Down Mode I 1) The typical values are measured at PDP I 2) The maximum values are measured at PDP has a maximum value of 200 ...
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Table 43 Power Supply Current Parameters (Operating Conditions apply 3.3V range) DDP Parameter V = 3.3V Range DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled I 1) The typical values are ...
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Table 44 Power Down Current (Operating Conditions apply; range) Parameter V = 3.3V Range DDP Power-Down Mode I 1) The typical values are measured at PDP I 2) The maximum values are measured at PDP has a maximum value of ...
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AC Parameters The electrical characteristics of the AC Parameters are detailed in this section. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 40, Figure 41 V DDP 10% ...
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Output Rise/Fall Times Table 45 provides the characteristics of the output rise/fall times in the XC886/888. Table 45 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Range DDP Rise/fall times V = 3.3V Range DDP Rise/fall ...
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Power-on Reset and PLL Timing Table 49 provides the characteristics of the power-on reset and PLL timing in the XC886/888. Table 46 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Pad operating voltage On-Chip Oscillator start-up time Flash ...
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VDDP V PAD VDDC OSC PLL Flash State t RST RESET Pads 2) 1) 1)Pad state undefined I)until EVR is stable Figure 44 Power-on Reset Timing Data Sheet t OSCST PLL unlock t LOCK Reset Initialization 3) 2)ENPS control 3)As ...
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On-Chip Oscillator Characteristics Table 47 provides the characteristics of the on-chip oscillator in the XC886/888. Table 47 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol f Nominal frequency NOM ∆ f Long term frequency LT deviation ∆ f Short ...
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External Clock Drive XTAL1 Table 48 shows the parameters that define the external clock supply for XC886/888. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal ...
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JTAG Timing Table 49 provides the characteristics of the JTAG timing in the XC886/888. Table 49 TCK Clock Timing (Operating Conditions apply pF) Parameter TCK clock period TCK high time TCK low time TCK clock rise ...
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Table 50 JTAG Timing (Operating Conditions apply pF) (cont’d) Parameter TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK 1) Not all parameters are 100% tested, but are verified by ...
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SSC Master Mode Timing Table 51 provides the characteristics of the SSC timing in the XC886/888. Table 51 SSC Master Mode Timing (Operating Conditions apply pF) Parameter SCLK clock period MTSR delay from SCLK MRST setup ...
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Package and Quality Declaration Chapter 5 provides the information of the XC886/888 package and reliability section. 5.1 Package Parameters Table 1 provides the thermal characteristics of the package used in XC886 and XC888. Table 1 Thermal Characteristics of the ...
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Package Outline Figure 48 shows the package outlines of the XC886. 0.5 5.5 2) 0.22 ±0. Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does ...
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Figure 49 shows the package outlines of the XC888. Figure 49 PG-TQFP-64 Package Outline Data Sheet Package and Quality Declaration 135 XC886/888CLM V1.2, 2009-07 ...
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Quality Declaration Table 2 shows the characteristics of the quality parameters in the XC886/888. Table 2 Quality Parameters Parameter ESD susceptibility according to Human Body Model (HBM) ESD susceptibility according to Charged Device Model (CDM) pins 1) Not all ...
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