UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website: http://www.renesas.com
Old Company Name in Catalogs and Other Documents
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for UPD78F1152AGC-GAD-AX

UPD78F1152AGC-GAD-AX Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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User’s Manual 78K0R/KF3 16-bit Single-Chip Microcontrollers μ PD78F1152, 78F1152A, 78F1152A(A) μ PD78F1153, 78F1153A, 78F1153A(A) μ PD78F1154, 78F1154A, 78F1154A(A) μ PD78F1155, 78F1155A, 78F1155A(A) μ PD78F1156, 78F1156A, 78F1156A(A) Document No. U17893EJ8V0UD00 (8th edition) Date Published September 2009 NS 2006 Printed in Japan ...

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User’s Manual U17893EJ8V0UD ...

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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

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Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. EEPROM is a trademark of NEC Electronics Corporation. SuperFlash is a registered ...

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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0R/KF3 and design and develop application systems and programs for these de- vices. The target products are as follows. • Conventional-specification products of the ...

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How to interpret the register format: → For a bit number enclosed in angle brackets, the bit name is defined as a re- served word in the RA78K0R, and is defined as an sfr variable using the #pragma sfr ...

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Documents Related to Flash Memory Programming PG-FP4 Flash Memory Programmer User’s Manual PG-FP5 Flash Memory Programmer Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. ...

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CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 Differences Between Conventional-Specification Products ( Specification Products ( 1.2 Features......................................................................................................................................... 18 1.3 Applications .................................................................................................................................. 19 1.4 Ordering Information.................................................................................................................... 19 1.5 Pin Configuration (Top View) ...................................................................................................... 20 1.6 78K0R/Kx3 Microcontroller Lineup............................................................................................. 22 1.7 Block Diagram ...

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Extended special function register (2nd SFR: 2nd Special Function Register) area ........................59 3.1.6 Data memory addressing ..................................................................................................................60 3.2 Processor Registers .................................................................................................................... 65 3.2.1 Control registers................................................................................................................................65 3.2.2 General-purpose registers ................................................................................................................67 3.2.3 ES and CS registers .........................................................................................................................69 3.2.4 Special function registers ...

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CHAPTER 5 CLOCK GENERATOR .................................................................................................... 151 5.1 Functions of Clock Generator................................................................................................... 151 5.2 Configuration of Clock Generator ............................................................................................ 152 5.3 Registers Controlling Clock Generator.................................................................................... 154 5.4 System Clock Oscillator ............................................................................................................ 168 5.4.1 X1 oscillator.....................................................................................................................................168 5.4.2 XT1 oscillator ..................................................................................................................................168 5.4.3 Internal ...

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Operation as one-shot pulse output function...................................................................................259 6.8.3 Operation as multiple PWM output function ....................................................................................266 CHAPTER 7 REAL-TIME COUNTER .................................................................................................. 273 7.1 Functions of Real-Time Counter............................................................................................... 273 7.2 Configuration of Real-Time Counter ........................................................................................ 273 7.3 Registers Controlling Real-Time Counter ............................................................................... ...

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Procedures for using temperature sensors ...................................................................................334 10.6 How to Read A/D Converter Characteristics Table............................................................... 337 10.7 Cautions for A/D Converter ..................................................................................................... 339 CHAPTER 11 D/A CONVERTER ......................................................................................................... 344 11.1 Function of D/A Converter....................................................................................................... 344 11.2 Configuration of D/A Converter ...

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Relationship Between Register Settings and Pins ............................................................... 487 CHAPTER 13 SERIAL INTERFACE IIC0 ........................................................................................... 494 13.1 Functions of Serial Interface IIC0 ........................................................................................... 494 13.2 Configuration of Serial Interface IIC0..................................................................................... 497 13.3 Registers to Controlling Serial Interface IIC0........................................................................ 500 2 ...

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UART consecutive reception + ACK transmission ........................................................................589 15.5.6 Holding DMA transfer pending by DWAITn ...................................................................................591 15.5.7 Forced termination by software .....................................................................................................592 15.6 Cautions on Using DMA Controller ........................................................................................ 594 CHAPTER 16 INTERRUPT FUNCTIONS ............................................................................................ 597 16.1 Interrupt Function Types ...

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CHAPTER 22 REGULATOR ................................................................................................................. 674 22.1 Regulator Overview ................................................................................................................. 674 22.2 Registers Controlling Regulator............................................................................................. 674 CHAPTER 23 OPTION BYTE............................................................................................................... 676 23.1 Functions of Option Bytes ...................................................................................................... 676 23.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) .........................................................676 23.1.2 On-chip debug ...

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CHAPTER 27 INSTRUCTION SET........................................................................................................ 705 27.1 Conventions Used in Operation List ...................................................................................... 706 27.1.1 Operand identifiers and specification methods..............................................................................706 27.1.2 Description of operation column....................................................................................................707 27.1.3 Description of flag operation column .............................................................................................708 27.1.4 PREFIX Instruction........................................................................................................................708 27.2 Operation List ........................................................................................................................... 709 CHAPTER ...

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Differences Between Conventional-Specification Products ( Specification Products ( This manual describes the functions of the 78K0R/KF3 microcontroller products with conventional specifications μ ( PD78F115x) and expanded specifications ( The differences between the conventional-specification products ( μ products ( PD78F115xA) ...

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Features Minimum instruction execution time can be changed from high speed (0.05 speed system clock) to ultra low-speed (61 General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Item Part ...

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Applications Home appliances • Laser printer motors • Clothes washers • Air conditioners • Refrigerators Home audio systems Digital cameras, digital video cameras 1.4 Ordering Information • Flash memory version (lead-free products) Part Number μ PD78F1152GC-GAD-AX μ PD78F1152AGC-GAD-AX μ ...

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Pin Configuration (Top View) • 80-pin plastic LQFP (14 × 14) • 80-pin plastic LQFP (fine pitch) (12 × 12 P120/INTP0/EXLVI 2 P47 3 P46 ...

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Pin Identification ANI0 to ANI7: Analog input ANO0, ANO1: Analog output Analog reference voltage REF0, REF1 AV : Analog ground Power supply for port Ground for port SS EXCLK: External clock ...

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Microcontroller Lineup ROM RAM 78K0R/KE3 64 Pins − 512 − 384 μ 256 PD78F1146 μ PD78F1146A μ 192 PD78F1145 μ PD78F1145A μ 128 ...

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Block Diagram TIMER ARRAY UNIT (8ch) TI00/P00 ch0 TO00/P01 TI01/TO01/P16 ch1 ch2 TI02/TO02/P17 ch3 TI03/TO03/P31 TI04/TO04/P42 ch4 TI05/TO05/P05 ch5 TI06/TO06/P06 ch6 TI07/TO07/P145 ch7 RxD3/P14 (LINSEL) LOW-SPEED INTERNAL OSCILLATOR WINDOW WATCHDOG TIMER RTCDIV/RTCCL/P15 REALTIME COUNTER RTC1HZ/P30 SERIAL ARRAY UNIT0 (4ch) ...

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Outline of Functions μ Item μ Internal Flash memory 64 KB memory (self-programming supported) RAM 4 KB Memory space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock ...

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Item μ PD78F1152A • UART supporting LIN-bus: 1 channel Serial interface • CSI: 2 channels/UART: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I • CSI: 1 channel/UART: 1 channel/simplified I • bits × 16 bits = ...

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Pin Function List There are four types of pin I/O buffer power supplies: AV these power supplies and the pins is shown below. Power Supply AV REF0 AV REF1 CHAPTER 2 PIN FUNCTIONS , ...

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Port functions (1/2) Function Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input of P03 and P04 can be set to TTL input buffer. P02 Output of P02 to P04 can be set to N-ch open-drain output ...

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Port functions (2/2) Function Name I/O P60 I/O Port 6. 8-bit I/O port. P61 Output of P60 to P63 can be set to N-ch open-drain output (6 P62 V tolerance). P63 Input/output can be specified in 1-bit units. For ...

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Non-port functions (1/3) Function Name I/O ANI0 to ANI7 Input A/D converter analog input ANO0 Output D/A converter analog output ANO1 Output D/A converter analog output EXLVI Input Potential input for external low-voltage detection INTP0 Input External interrupt request ...

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Non-port functions (2/3) Function Name I/O SCL0 I/O Clock input/output for I SCL10 I/O Clock input/output for simplified I SCL20 I/O Clock input/output for simplified I SDA0 I/O Serial data I/O for I SDA10 Serial data I/O for simplified ...

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Non-port functions (3/3) Function Name I/O − V Positive power supply (P121 to P124 and other than ports DD (excluding RESET and FLMD0 pins)) − EV Positive power supply for ports (other than P20 to P27, P110, DD P111 ...

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Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, and clock I/O. Input to the P03 and P04 ...

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Caution To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial communication operation setting register 02 (SCR02) to the default status (0087H). In addition, clear port output mode register 0 (POM0) to 00H. 2.2.2 P10 to P17 (port 1) P10 ...

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TO01, TO02 These are the timer output pins of 16-bit timers 01 and 02. (j) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) ...

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Control mode P30 and P31 function as external interrupt request input, timer I/O, and real-time counter correction clock output. (a) INTP3, INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, ...

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TOOL1 This is a clock output pin for a debugger. When the on-chip debug function is used, P41/TOOL1 pin can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port ...

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Control mode P50, P51 function as external interrupt request input. (a) INTP1, INTP2 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. ...

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P90 (port 9) P90 function as an 1-bit I/O port. The port mode can be specified in 1-bit units. (1) Port mode P90 function as an 1-bit I/O port. P90 can be set to input or output port in ...

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XT1, XT2 These are the pins for connecting a resonator for subsystem clock. 2.2.12 P130 (port 13) P130 functions as a 1-bit output port. Remark When the device is reset, P130 outputs a low level. Therefore, to output a ...

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SCK20 This is a serial clock I/O pin of serial interface CSI20. (h) TxD2 This is a serial data output pin of serial interface UART2. (i) RxD2 This is a serial data input pin of serial interface UART2. (j) ...

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AV REF1 This is the D/A converter reference voltage input pin and the positive power supply pin of P110, P111, and D/A converter. The voltage that can be supplied to AV used as digital I/Os or analog inputs. Table ...

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the positive power supply pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0 DD pins the positive power supply pin for ports other than ...

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Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins. Table 2-4. Connection of Unused Pins (1/3) Pin Name I/O Circuit Type P00/TI00 8-R ...

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Table 2-4. Connection of Unused Pins (2/3) Pin Name I/O Circuit Type P50/INTP1 8-R P51/INTP2 P52 to P55 5-AG P60/SCL0 13-R P61/SDA0 P62, P63 13-P P64 to P67 5-AG P70/KR0 to P73/KR3 8-R P74/KR4/INTP8 to P77/KR7/INTP11 P90 5-AG P110/ANO0, P111/ANO1 ...

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Table 2-4. Connection of Unused Pins (3/3) Pin Name I/O Circuit Type − AV REF1 − FLMD0 2-W RESET 2 − REGC CHAPTER 2 PIN FUNCTIONS I/O Recommended Connection of Unused Pins − Make this pin the same ...

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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 2 P-ch N- Schmitt-triggered input with hysteresis characteristics Type 3-C EV Data EV 46 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type ...

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Type 11-G AV Data Output disable P-ch Comparator + _ N-ch Series resistor string voltage AV SS Input enable Type 12-G AV REF1 Data P-ch Output N-ch disable AV SS Input enable P-ch Output analog voltage N-ch Type 13-P Data ...

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Memory Space Products in the 78K0R/KF3 can access memory space. Figures 3-1 to 3-5 show the memory maps. Figure 3-1. Memory Map ( Special function register (SFR ...

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Figure 3-2. Memory Map ( Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

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Figure 3-3. Memory Map ( Special function register (SFR General-purpose register 32 bytes ...

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Figure 3-4. Memory Map ( Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

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Figure 3-5. Memory Map ( Special function register (SFR General-purpose register 32 bytes ...

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Remark The flash memory is divided into blocks (one block = 2 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory ...

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Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Address Value Number 00000H to 007FFH 00H 10000H to 107FFH ...

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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0R/KF3 products incorporate internal ROM (flash memory), as shown below. Part Number μ PD78F1152, 78F1152A ...

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Vector Table Address Interrupt Source 00000H RESET input, POC, LVI, WDT, TRAP 00004H INTWDTI 00006H INTLVI 00008H INTP0 0000AH INTP1 0000CH INTP2 0000EH INTP3 00010H INTP4 00012H INTP5 00014H INTST3 00016H INTSR3 00018H INTSRE3 0001AH INTDMA0 0001CH INTDMA1 0001EH INTST0/INTCSI00 ...

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Mirror area μ The PD78F1152 and 78F1152A mirror the data flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. μ The PD78F1153, 78F1153A, 78F1154, 78F1154A, 78F1155, 78F1155A, 78F1156, 78F1156A mirror the data flash area of 00000H to 0FFFFH ...

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Processor mode control register (PMC) This register selects the flash memory space for mirroring to area from F0000H to FFFFFH. PMC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to ...

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Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not ...

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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...

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Figure 3-8. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

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Figure 3-9. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

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Figure 3-10. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

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Figure 3-11. Correspondence Between Data Memory and Addressing ( <R> Special function register (SFR 256 bytes ...

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Processor Registers The 78K0R/KF3 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...

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Auxiliary carry flag (AC) If the operation result has a carry from bit borrow at bit 3, this flag is set (1 reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) ...

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Figure 3-15. Data to Be Saved to Stack Memory PUSH rp instruction SP←SP−2 ↑ Register pair lower SP−2 ↑ SP−1 Register pair higher ↑ → SP CALL, CALLT instructions (4-byte stack) SP←SP−4 ↑ PC7 to PC0 SP−4 ↑ SP−3 PC15 ...

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Figure 3-16. Configuration of General-Purpose Registers FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H ...

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ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is ...

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Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable ...

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Address Special Function Register (SFR) Name FFF00H Port register 0 FFF01H Port register 1 FFF02H Port register 2 FFF03H Port register 3 FFF04H Port register 4 FFF05H Port register 5 FFF06H Port register 6 FFF07H Port register 7 FFF09H Port ...

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Address Special Function Register (SFR) Name FFF30H A/D converter mode register FFF31H Analog input channel specification register FFF32H D/A converter mode register FFF37H Key return mode register FFF38H External interrupt rising edge enable register 0 FFF39H External interrupt falling edge ...

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Address Special Function Register (SFR) Name FFF90H Sub-count register FFF91H FFF92H Second count register FFF93H Minute count register FFF94H Hour count register FFF95H Week count register FFF96H Day count register FFF97H Month count register FFF98H Year count register FFF99H Watch ...

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Address Special Function Register (SFR) Name FFFB0H DMA SFR address register 0 FFFB1H DMA SFR address register 1 FFFB2H DMA RAM address register 0L FFFB3H DMA RAM address register 0H FFFB4H DMA RAM address register 1L FFFB5H DMA RAM address ...

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Address Special Function Register (SFR) Name FFFEEH Priority specification flag register 11L FFFEFH Priority specification flag register 11H FFFF0H Multiplication input data register A FFFF1H FFFF2H Multiplication input data register B FFFF3H FFFF4H Higher multiplication result storage register FFFF5H FFFF6H ...

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Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the ...

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Table 3-6. Extended SFR (2nd SFR) List (1/5) Address Special Function Register (SFR) Name F0017H A/D port configuration register F0030H Pull-up resistor option register 0 F0031H Pull-up resistor option register 1 F0033H Pull-up resistor option register 3 F0034H Pull-up resistor ...

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Table 3-6. Extended SFR (2nd SFR) List (2/5) Address Special Function Register (SFR) Name F0110H Serial mode register 00 F0111H F0112H Serial mode register 01 F0113H F0114H Serial mode register 02 F0115H F0116H Serial mode register 03 F0117H F0118H Serial ...

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Table 3-6. Extended SFR (2nd SFR) List (3/5) Address Special Function Register (SFR) Name F014CH Serial flag clear trigger register 12 F014DH F014EH Serial flag clear trigger register 13 F014FH F0150H Serial mode register 10 F0151H F0152H Serial mode register ...

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Table 3-6. Extended SFR (2nd SFR) List (4/5) Address Special Function Register (SFR) Name F0188H Timer counter register 04 F0189H F018AH Timer counter register 05 F018BH F018CH Timer counter register 06 F018DH F018EH Timer counter register 07 F018FH F0190H Timer ...

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Table 3-6. Extended SFR (2nd SFR) List (5/5) Address Special Function Register (SFR) Name F01B0H Timer enable status register 0 F01B1H F01B2H Timer start trigger register 0 F01B3H F01B4H Timer stop trigger register 0 F01B5H F01B6H Timer clock select register ...

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Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the ...

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Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address ...

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Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies ...

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Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] ...

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Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is ...

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Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier SADDR Label, FFE20H ...

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SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFR name SFRP ...

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Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier − [DE], [HL] (only the space from F0000H ...

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Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used ...

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CHAPTER 3 CPU ARCHITECTURE Figure 3-32. Example of [HL + byte], [DE + byte] rp (HL/DE) OP code byte Figure 3-33. Example of word[B], word[C] r (B/C) OP code Low Addr. High Addr. Figure 3-34. Example of word[BC] rp (BC) ...

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Figure 3-35. Example of ES:[HL + byte], ES:[DE + byte] OP code byte Figure 3-36. Example of ES:word[B], ES:word[C] OP code Low Addr. High Addr. OP code Low Addr. High Addr. 92 CHAPTER 3 CPU ARCHITECTURE ES rp (HL/DE) Target ...

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Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word ...

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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of ...

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Port Functions There are four types of pin I/O buffer power supplies: AV these power supplies and the pins is shown below. Power Supply AV REF0 AV REF1 78K0R/KF3 products are provided with the ports ...

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Function Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input of P03 and P04 can be set to TTL input buffer. P02 Output of P02 to P04 can be set to N-ch open-drain output P03 (V tolerance). DD ...

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Function Name I/O P60 I/O Port 6. 8-bit I/O port. P61 Output of P60 to P63 can be set to N-ch open-drain output (6 P62 V tolerance). P63 Input/output can be specified in 1-bit units. For only P64 to P67, ...

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Port Configuration Ports include the following hardware. Item Control registers Port mode registers (PM0 to PM7, PM9, PM11, PM12, PM14) Port registers (P0 to P7, P9, P11 to P14) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, ...

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Port 0 Port 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 ...

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WR PU PU0 PU01 RD WR PORT P0 Output latch (P01 PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal 100 CHAPTER ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 WR PU PU0 PU02 RD WR PORT P0 Output latch (P02) WR POM POM0 POM02 WR PM PM0 PM02 Alternate function P0: Port register 0 PU0: Pull-up resistor option register ...

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Figure 4-5. Block Diagram of P03 and P04 WR PIM PIM0 PIM03, PIM04 WR PU PU0 PU03, PU04 Alternate function RD WR PORT P0 Output latch (P03, P04) WR POM POM0 POM03, POM04 WR PM PM0 PM03, PM04 Alternate function ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P05 and P06 WR PU PU0 PU05, PU06 Alternate function RD WR PORT P0 Output latch (P05, P06 PM0 PM05, PM06 Alternate function P0: Port register 0 PU0: Pull-up ...

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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P10 WR PU PU1 PU10 Alternate function RD WR PORT P1 Output latch (P10 PM1 PM10 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: ...

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Figure 4-8. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT P1 Output latch (P11, P14 PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P12 and P13 WR PU PU1 PU12, PU13 RD WR PORT P1 Output latch (P12, P13 PM1 PM12, PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option ...

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WR PU PU1 PU15 RD WR PORT P1 Output latch (P15 PM1 PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal 108 CHAPTER ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT P1 Output latch (P16, P17 PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up ...

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Port 2 Port 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be ...

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Figure 4-12. Block Diagram of P20 to P27 RD WR PORT P2 Output latch (P20 to P27 PM2 PM20 to PM27 P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR××: Write signal 4.2.4 Port ...

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Figure 4-13. Block Diagram of P30 and P31 WR PU PU3 PU30, PU31 Alternate function RD WR PORT P3 Output latch (P30, P31 PM3 PM30, PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 ...

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Port 4 Port 8-bit I/O port with a output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 ...

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WR PU PU4 PU40 Alternate function RD WR PORT P4 Output latch (P40 PM4 PM40 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P41 WR PU PU4 PU41 RD WR PORT P4 Output latch (P41 PM4 PM41 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode ...

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WR PU PU4 PU42 Alternate function RD WR PORT P4 Output latch (P42 PM4 PM42 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P43 WR PIM PIM4 PIM43 WR PU PU4 PU43 Alternate function RD WR PORT P4 Output latch (P43) WR POM POM4 POM43 WR PM PM4 PM43 Alternate function P4: Port register ...

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WR PIM PIM4 PIM44 WR PU PU4 PU44 Alternate function RD WR PORT P4 Output latch (P44 PM4 PM44 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PIM4: Port input mode ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P45 WR PU PU4 PU45 RD WR PORT P4 Output latch (P45) WR POM POM4 POM45 WR PM PM4 PM45 Alternate function P4: Port register 4 PU4: Pull-up resistor option register ...

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Figure 4-20. Block Diagram of P46 and P47 WR PU PU4 PU46, PU47 RD WR PORT P4 Output latch (P46, P47 PM4 PM46, PM47 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register ...

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Port 5 Port 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P55 ...

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Figure 4-22. Block Diagram of P52 to P55 WR PU PU5 PU52 to PU55 RD WR PORT P5 Output latch (P52 to P55 PM5 PM52 to PM55 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: ...

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Port 6 Port 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 ...

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Figure 4-24. Block Diagram of P62 and P63 RD WR PORT Output latch (P62, P63 PM6 PM62, PM63 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WR××: Write signal 124 CHAPTER 4 PORT FUNCTIONS ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P64 to P67 WR PU PU6 PU64 to PU67 RD WR PORT P6 Output latch (P64 to P67 PM6 PM64to PM67 P6: Port register 6 PU6: Pull-up resistor option ...

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Port 7 Port 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input ...

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Port 9 Port 1-bit I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). When the P90 pin is ...

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Port 11 Port 2-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). This port can also be ...

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Port 12 P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, ...

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Figure 4-30. Block Diagram of P121 and P122 RD RD CMC: Clock operation mode control register RD: Read signal 130 CHAPTER 4 PORT FUNCTIONS Clock generator CMC OSCSEL CMC EXCLK, OSCSEL User’s Manual U17893EJ8V0UD P122/X2/EXCLK P121/X1 ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of P123 and P124 Clock generator RD RD CMC: Clock operation mode control register RD: Read signal User’s Manual U17893EJ8V0UD CMC OSCSELS CMC OSCSELS P124/XT2 P123/XT1 131 ...

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Port 13 P130 is a 1-bit output-only port with an output latch. Figure 4-32 shows block diagrams of port 13 PORT Output latch P13: Port register 13 RD: Read signal WR××: Write signal Remark When reset is ...

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Port 14 Port 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 ...

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Figure 4-33. Block Diagram of P140, P141, and P145 WR PU PU14 PU140, PU141, PU145 Alternate function RD WR PORT P14 Output latch (P140, P141, P145 PM14 PM140, PM141, P145 Alternate function P14: Port register 14 PU14: Pull-up ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of P142 and P143 WR PIM PIM14 PIM142, PIM143 WR PU PU14 PU142, PU143 Alternate function RD WR PORT P14 Output latch (P142, P143) WR POM POM14 POM142, POM143 WR PM PM14 ...

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WR PU PU14 PU144 RD WR PORT P14 Output latch (P144) WR POM POM14 POM144 WR PM PM14 PM144 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 POM14: Port output mode ...

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Registers Controlling Port Function Port functions are controlled by the following six types of registers. • Port mode registers (PM0 to PM7, PM9, PM11, PM12, PM14) • Port registers (P0 to P7, P9, P11 to P14) • Pull-up resistor ...

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Figure 4-36. Format of Port Mode Register Symbol PM0 1 PM06 PM05 PM1 PM17 PM16 PM15 PM2 PM27 PM26 PM25 PM3 PM4 PM47 PM46 PM45 PM5 1 1 PM55 PM6 PM67 PM66 PM65 PM7 ...

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Port registers (P0 to P7, P9, P11 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level ...

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Symbol P06 P05 P1 P17 P16 P15 P2 P27 P26 P25 P47 P46 P45 P55 P6 P67 P66 P65 P7 P77 P76 P75 ...

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Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, PU12, PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P55, P64 to P67, P70 ...

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Port input mode registers (PIM0, PIM4, PIM14) These registers set the input buffer of P03, P04, P43, P44, P142, or P143 in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the ...

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A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...

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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...

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Connecting to external device with different power potential (2 When parts of ports 0, 4, and 14 operate with V operates power supply voltage are possible. Regarding inputs, CMOS/TTL ...

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Setting procedure when using I/O pins of simplified IIC10 and IIC20 functions <1> After reset release, the port mode is the input mode (Hi-Z). <2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). ...

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Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table 4-5. Settings of Port ...

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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/3) Pin Name Function Name Note 1 Note 1 P20 to P27 ANI0 to ANI7 P30 RTC1HZ INTP3 P31 TI03 TO03 INTP4 P40 TOOL0 P41 TOOL1 ...

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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (3/3) Pin Name Function Name P143 SI20 RxD2 SDA20 P144 SO20 TxD2 P145 TI07 TO07 Remark ×: don’t care PM××: Port mode register P××: Port output ...

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Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...

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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This ...

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Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Clock operation mode control register (CMC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) ...

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Clock operation mode Clock operation status control register control register (CMC) (CSC) AMPH EXCLK OSCSEL MSTOP STOP High-speed system clock oscillator f MX X1/P121 Crystal/ceramic f X oscillation X2/EXCLK Internal /P122 External input f EX high-speed f clock IH oscillator ...

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Remark clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency High-speed system clock frequency Main system clock frequency MAIN <R> f ...

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Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins, and to select a gain of the oscillator. CMC can be written only once by an ...

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Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the internal low-speed oscillation clock). CSC can be set by a 1-bit ...

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Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock • CLS = 0 and MCS = 0 X1 clock • CLS = 1 External main system (CPU and peripheral hardware clocks operate with a clock clock other than ...

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Figure 5-4. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST ...

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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits ...

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Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol 7 6 OSTS 0 0 OSTS2 OSTS1 Cautions ...

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System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a division ratio. CKC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 09H. ...

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Cautions 1. Be sure to set bit The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to ...

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Peripheral enable registers 0 (PER0) These registers are used to enable or disable use of each peripheral hardware macro. Clock supply to the hardware that is not used is also stopped decrease the power consumption and ...

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Figure 5-7. Format of Peripheral Enable Register (2/2) SAU1EN 0 Stops input clock supply. • SFR used by the serial array unit 1 cannot be written. • The serial array unit the reset status. 1 Supplies input ...

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Operation speed mode control register (OSMC) This register is used to control the step-up circuit of the flash memory for high-speed operation. If the microcontroller operates at a low speed with a system clock of 10 MHz or less, ...

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Internal high-speed oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the internal high-speed oscillator. With self-measurement of the internal high-speed oscillator frequency via a subsystem clock using a crystal resonator, a timer using high-accuracy ...

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Figure 5-9. Format of Internal High-Speed Oscillator Trimming Register (HIOTRM) Address: F00F2H After reset: 10H Symbol 7 6 HIOTRM 0 0 TTRM4 TTRM3 ...

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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input ...

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Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as ...

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Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, ...

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Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0R/KF3 (8 MHz (TYP.)). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). After a reset release, the internal high-speed oscillator ...

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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). • Main system clock f MAIN • High-speed system clock clock ...

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Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1)) Power supply 1.8 V voltage ( 1.59 V (TYP.) 0.5 V/ms (MIN.) 0 ...

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Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 ...

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Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. 2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation ...

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Controlling Clock 5.6.1 Example of controlling high-speed system clock The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected to the X1 and X2 pins. • External main system clock: External clock ...

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Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register) EXCLK OSCSEL 1 1 Remarks 1. ×: don’t care 2. For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 ...

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If some peripheral hardware macros are not used, supply of the input clock to each hardware macro can be stopped. (PER0 register) RTCEN DACEN xxxEN 0 Stops input clock supply. 1 Supplies input clock. Caution Be sure to clear ...

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To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (CKC register) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system ...

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Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock and setting the division ratio of the set clock (CKC register) MCM0 MDIV2 Caution If switching the ...

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Stopping the internal high-speed oscillation clock (CSC register) When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP ...

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Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillation (See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.) Note The setting of <1> is not necessary when ...

Page 185

Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Used only as the watchdog timer clock. The internal low-speed oscillator automatically starts oscillation after a reset release, and the ...

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CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram Internal high-speed oscillation: Operating Internal high-speed oscillation: X1 oscillation/EXCLK input: Selectable by CPU Selectable by ...

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Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status ...

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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) → ...

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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) → ...

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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4) <R> (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) → (C) ...

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Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock speed oscillation ...

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CPU Clock Before Change After Change Subsystem Internal high- Oscillation of internal high-speed oscillator Note clock speed oscillation and selection of internal high-speed clock oscillation clock as main system clock • HIOSTOP = 0, MCS = 0 X1 clock Stabilization ...

Page 193

Time required for switchover of CPU clock and main system clock By setting bits and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between ...

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Table 5-9. Maximum Number of Clocks Required in Type 3 Set Value Before Switchover CSS CLK MAINC CLK SUB <R> Remarks 1. f :Internal high-speed oscillation clock frequency IH f :High-speed ...

Page 195

The timer array unit has eight 16-bit timers per unit. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. Single-operation ...

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Functions of each channel when it operates with another channel Combination-operation functions are those functions that are attained by using the master channel (mostly the reference timer that controls cycles) and the slave channels (timers that operate following the ...

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Configuration of Timer Array Unit The timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Timer/counter Timer counter register 0n (TCR0n) Register Timer data register 0n (TDR0n) Timer input TI00 to TI07 pins, ...

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Peripheral enable TAU0EN PRS013 PRS012 PRS011 PRS010 register 0 (PER0) f CLK TI00/P00 Channel 0 CK00 MCK CK01 f /4 SUB Edge detection TIS01 TNFEN01 TI01/P16/ T01/INTP5 (Timer input pin) Channel 1 TI02/P17/ Channel 2 TO02 TI03/P31/ Channel 3 TO03/INTP4 ...

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Timer/counter register 0n (TCR0n) TCR0n is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is ...

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The TCR0n register read value differs as follows according to operation mode changes and the operating status. Table 6-2. TCR0n Register Read Value in Various Operation Modes Operation Mode Count Mode Operation mode change after reset Interval timer Count down ...

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