UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 146

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Clock operation status control register (CSC)
144
This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock,
and subsystem clock (except the internal low-speed oscillation clock).
CSC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Address: FFFA1H
Symbol
CSC
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
HIOSTOP
XTSTOP
MSTOP
MSTOP
<7>
Figure 5-3. Format of Clock Operation Status Control Register (CSC)
0
1
0
1
0
1
After reset: C0H
2. To start X1 oscillation as set by MSTOP, check the oscillation stabilization time
3. Do not stop the clock selected for the CPU/peripheral hardware clock (f
4. The setting of the flags of the register to stop clock oscillation (invalidate the
X1 oscillator operating
X1 oscillator stopped
XT1 oscillator operating
XT1 oscillator stopped
Internal high-speed oscillator operating
Internal high-speed oscillator stopped
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
the OSC register.
external clock input) and the condition before clock oscillation is to be stopped
are as shown in Table 5-2.
XTSTOP
<6>
X1 oscillation mode
XT1 oscillation mode
CHAPTER 5 CLOCK GENERATOR
R/W
User’s Manual U17854EJ9V0UD
5
0
Internal high-speed oscillation clock operation control
High-speed system clock operation control
Subsystem clock operation control
External clock from EXCLK
pin is valid
External clock from EXCLK
pin is invalid
4
0
External clock input mode
3
0
2
0
Input port mode
−
Input port mode
1
0
−
HIOSTOP
<0>
CLK
) with