UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 151

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
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RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
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(5) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
(Cautions 1 to 3 are listed on the next page.)
Address: FFFA4H
Symbol
CKC
Notes 1. Bits 7 and 5 are read-only.
Remarks 1. f
MCS
1
CSS
CLS
CLS
<7>
Note 3
0
1
0
1
0
0
2. Setting is prohibited when f
3. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
After reset: 09H
2. ×:
Figure 5-6. Format of System Clock Control Register (CKC)
Main system clock (f
Subsystem clock (f
Internal high-speed oscillation clock (f
High-speed system clock (f
f
f
IH
MX
SUB
MCM0
:
×
: High-speed system clock frequency
CSS
<6>
: Subsystem clock frequency
Note 3
0
1
Internal high-speed oscillation clock frequency
don’t care
Other than above
CHAPTER 5 CLOCK GENERATOR
R/W
MDIV2
MCS
<5>
User’s Manual U17854EJ9V0UD
Note 1
0
0
0
0
1
1
0
0
0
0
1
1
×
SUB
MAIN
)
Status of CPU/peripheral hardware clock (f
)
MX
MX
Status of Main system clock (f
MDIV1
)
MCM0
< 4 MHz.
<4>
0
0
1
1
0
0
0
0
1
1
0
0
×
IH
)
MDIV0
0
1
0
1
0
1
0
1
0
1
0
1
×
3
1
f
f
f
f
f
f
f
f
f
f
f
f
f
Setting prohibited
IH
IH
IH
IH
IH
IH
MX
MX
MX
MX
MX
MX
SUB
/2 (default)
/2
/2
/2
/2
MDIV2
/2
/2
/2
/2
/2
/2
2
3
4
5
2
3
4
5 Note 2
2
MAIN
Selection of CPU/peripheral
)
hardware clock (f
CLK
)
MDIV1
1
CLK
)
MDIV0
0
149

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