UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 171

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
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Part Number:
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5.6.3 Example of controlling subsystem clock
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
(1) Example of setting procedure when oscillating the subsystem clock
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
<1> Setting P123/XT1 and P124/XT2 pins (CMC register)
<2> Controlling oscillation of subsystem clock (CSC register)
<3> Waiting for the stabilization of the subsystem clock oscillation
Caution The CMC register can be written only once after reset release, by an 8-bit memory
<2> Stopping the internal high-speed oscillation clock (CSC register)
Remarks
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
peripheral hardware (except the real-time counter, clock output/buzzer output, and watchdog
timer). At this time, the operations of the A/D converter and IIC0 are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing the various
peripheral hardware as well as CHAPTER 27
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS).
EXCLK
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
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peripheral hardware that is operating on the internal high-speed oscillation clock.
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same
time.
oscillating the X1 clock or 5.6.1 (2) Example of setting procedure when using the external
main system clock.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting procedure when
OSCSEL
For setting of the P121/X1 and P122/X2 pins, see 5.6.1 Example of controlling high-
speed system clock.
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