UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 176

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
174
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
Status Transition
(B) → (D)
Status Transition
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(B) → (C)
(external main clock)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
Notes 1. The CMC and OSMC registers can be changed only once after reset release. This setting is not
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
Remark ×: don’t care
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-15.
(Setting sequence of SFR registers)
2. Set the oscillation stabilization time as follows.
3. FSEL = 1 when f
Setting Flag of SFR Register
(Setting sequence of SFR registers)
necessary if it has already been set.
(see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 28
ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
If a divided clock is selected and f
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/4)
Setting Flag of SFR Register
CLK
> 10 MHz
EXCLK
CHAPTER 5 CLOCK GENERATOR
Unnecessary if these registers
0
0
1
CMC Register
User’s Manual U17854EJ9V0UD
are already set
CMC Register
CLK
OSCSEL
OSCSELS
≤ 10 MHz, use with FSEL = 0 is possible even if f
1
1
1
1
Unnecessary if the CPU is operating
Note 1
AMPH
Note
with the subsystem clock
0
1
×
CSC Register
XTSTOP
Register
Note 2
Note 2
Note 2
OSTS
Unnecessary if the CPU is operating with
0
the high-speed system clock
MSTOP
Register
CSC
0
0
0
Stabilization
Waiting for
Necessary
Oscillation
OSMC
Register
FSEL
1
0/1
Note 3
0
Register
checked
checked
checked
Must be
Must be
OSTC
not be
Must
X
> 10 MHz.
CKC Register
CSS
MCM0
1
CKC
Regi
ster
1
1
1