UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 177

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
Status Transition
Status Transition
(C) → (D)
Status Transition
(D) → (B)
(C) → (B)
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-15.
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17854EJ9V0UD
Unnecessary if the CPU
CPU is operating with
CMC Register
Unnecessary if the CPU is operating with the subsystem
Unnecessary if the
is operating with the
internal high-speed
the internal high-
speed oscillation
OSCSELS
oscillation clock
CSC Register
CSC Register
HIOSTOP
HIOSTOP
1
clock
0
0
Note
CSC Register
XTSTOP
clock
register is already set
0
Oscillation accuracy
Unnecessary if this
stabilization time
10
MCM0
0
μ
s
Stabilization
Waiting for
Necessary
Oscillation
CKC Register
CKC Register
MCM0
CKC Register
CSS
0
0
CSS
1
175