UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 193

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
(3) Timer mode register 0n (TMR0n)
Symbol
TMR0n
TMR0n sets an operation mode of channel n. It is used to select an operation clock (MCK), a count clock,
whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the
timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting TMR0n is prohibited when the register is in operation (when TE0 = 1). However, bits 7 and 6
(CIS0n1, CIS0n0) can be rewritten even while the register is operating with some functions (when TE0 = 1) (for
details, see 6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural
Channels of Timer Array Unit).
TMR0n can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark
Operation clock MCK is used by the edge detector. A count clock (TCLK) is generated depending on the setting of
the CCS0n bit.
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
MAS
Only the even channel can be set as a master channel (MASTER0n = 1).
Be sure to use the odd channel as a slave channel (MASTER0n = 0).
Clear MASTER0n to 0 for a channel that is used with the single-operation function.
CKS
CCS
TER
CKS
0n
0n
0n
15
0n
0
1
0
1
0
1
n = 0 to 7, k = 0 to 6
Operation clock CK00 set by TPS0 register
Operation clock CK01 set by TPS0 register
Operation clock MCK specified by CKS0n bit
Valid edge of input signal input from TI0k pin/subsystem clock divided by 4 (f
Operates in single-operation function or as slave channel in combination-operation function.
Operates as master channel in combination-operation function.
14
0
Selection of operation in single-operation function or as slave channel in combination-operation function
Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (1/3)
13
0
CCS
12
0n
/operation as master channel in combination-operation function of channel n
MAST
ER0n
11
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
STS
0n2
Selection of operation clock (MCK) of channel n
10
Selection of count clock (TCLK) of channel n
STS
0n1
9
STS
0n0
8
After reset: 0000H
CIS
0n1
7
CIS
0n0
6
5
0
R/W
4
0
SUB
/4)
0n3
MD
3
0n2
MD
2
0n1
MD
1
0n0
MD
191
0

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