UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 196

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
194
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
(4) Timer status register 0n (TSR0n)
Symbol
TSR0n
TSR0n indicates the overflow status of the counter of channel n.
TSR0n is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to
MD0n1 = 110B). It will not be set in any other mode. See Table 6-3 for the operation of the OVF bit in each
operation mode and set/clear conditions.
TSR0n can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSR0n can be set with an 8-bit memory manipulation instruction with TSR0nL.
Reset signal generation clears this register to 0000H.
Remark
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
OVF
15
0
1
0
Table 6-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
Timer operation mode
Overflow does not occur.
Overflow occurs.
14
0
13
0
Figure 6-7. Format of Timer Status Register 0n (TSR0n)
12
0
11
0
CHAPTER 6 TIMER ARRAY UNIT
clear
set
clear
set
OVF
User’s Manual U17854EJ9V0UD
10
0
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
Counter overflow status of channel n
9
0
8
0
After reset: 0000H
(Use prohibited, not set and not cleared)
7
0
6
0
Set/clear conditions
5
0
R
4
0
3
0
2
0
1
0
OVF
0

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