UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 221

no-image

UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.7 Operation of Timer Array Unit as Independent Channel
6.7.1 Operation as interval timer/square wave output
(1) Interval timer
(2) Operation as square wave output
The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed
intervals.
The interrupt generation period can be calculated by the following expression.
A subsystem clock divided by four (f
Consequently, the interval timer can be operated with the count clock fixed to f
frequency (main system clock, subsystem clock). When changing the clock selected as f
value of the system clock control register (CKC)), however, stop the timer array unit (TAU) (TT0 = 00FFH) first.
TO0k performs a toggle operation as soon as INTTM0n has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TO0k can be calculated by the following
expressions.
TCR0n operates as a down counter in the interval timer mode.
TCR0n loads the value of TDR0n at the first count clock after the channel start trigger bit (TS0n) is set to 1. If
MD0n0 of TMR0n = 0 at this time, INTTM0n is not output and TO0k is not toggled. If MD0n0 of TMR0n = 1,
INTTM0n is output and TO0k is toggled.
After that, TCR0n count down in synchronization with the count clock.
When TCR0n = 0000H, INTTM0n is output and TO0k is toggled at the next count clock. At the same time,
TCR0n loads the value of TDR0n again. After that, the same operation is repeated.
TDR0n can be rewritten at any time. The new value of TDR0n becomes valid from the next period.
Remarks 1. n = 0 to 7, k = 0 to 6
Generation period of INTTM0n (timer interrupt) = Period of count clock × (Set value of TDR0n + 1)
• Period of square wave output from TO0k = Period of count clock × (Set value of TDR0n + 1) × 2
• Frequency of square wave output from TO0k = Frequency of count clock/{(Set value of TDR0n + 1) × 2}
2. f
f
CLK
SUB
: CPU/peripheral hardware clock frequency
: Subsystem clock oscillation frequency
CHAPTER 6 TIMER ARRAY UNIT
SUB
User’s Manual U17854EJ9V0UD
/4) can be selected as the count clock, in addition to CK00 and CK01.
SUB
/4, regardless of the f
CLK
(changing the
219
CLK

Related parts for UPD78F1144AGB-GAH-AX