UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 230

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.3 Operation as frequency divider (channel 0 only)
result from TO00.
detected. If MD000 of TMR00 = 0 at this time, INTTM00 is not output and TO00 is not toggled. If MD000 of TMR00 =
1, INTTM00 is output and TO00 is toggled.
time, TCR00 loads the value of TDR00 again, and continues counting.
period of the TO00 output.
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The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the
The divided clock frequency output from TO00 can be calculated by the following expression.
TCR00 operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) is set to 1, TCR00 loads the value of TDR00 when the TI00 valid edge is
After that, TCR00 counts down at the valid edge of TI0k. When TCR00 = 0000H, it toggles TO00. At the same
If detection of both the edges of TI00 is selected, the duty factor error of the input clock affects the divided clock
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
TDR00 can be rewritten at any time. The new value of TDR00 becomes valid during the next count period.
• When rising edge/falling edge is selected:
• When both edges are selected:
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
TI00 pin
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
TS00
detection
Edge
Figure 6-43. Block Diagram of Operation as Frequency Divider
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Timer counter
Data register
(TCR00)
(TDR00)
controller
Output
TO00 pin