UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 248

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

246
Operation
start
During
operation
Operation
stop
TAU stop
Remark
Sets TOE0m (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0m (slave) bits of the TS0
register are set to 1 at the same time.
Set values of the TMR0n and TMR0m registers, TOM0n,
TOM0m, TOL0n, and TOL0m bits cannot be changed.
Set values of the TDR0n and TDR0m registers can be
changed after INTTM0n of the master channel is
generated.
The TCR0n and TCR0m registers can always be read.
The TSR0n and TSR0m registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TT0n (master) and TT0m (slave) bits are set to 1 at
the same time.
TOE0m of slave channel is cleared to 0 and value is set
to the TO0m bit.
To hold the TO0m pin output levels
When holding the TO0m pin output levels is not
necessary
The TAU0EN bit of the PER0 register is cleared to 0.
Switches the port mode register to input mode.
n = 0, 2, 4
m = n + 1
The TS0n and TS0m bits automatically return to 0
because they are trigger bits.
The TT0n and TT0m bits automatically return to 0
because they are trigger bits.
Clears TO0m bit to 0 after the value to
be held is set to the port register.
Figure 6-59. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
TE0n = 1, TE0m = 1
The counter of the master channel loads the TDR0n value
to TCR0n, and counts down. When the count value
reaches TCR0n = 0000H, INTTM0n output is generated.
At the same time, the value of the TDR0n register is
loaded to TCR0n, and the counter starts counting down
again.
At the slave channel, the value of TDR0m is loaded to
TCR0m, triggered by INTTM0n of the master channel, and
the counter starts counting down. The output level of
TO0m becomes active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0m = 0000H, and the counting
operation is stopped.
After that, the above operation is repeated.
TE0n, TE0m = 0, and count operation stops.
The TO0m pin outputs the TO0n set level.
The TO0m pin output levels is held by port function.
The TO0m pin output levels go are into Hi-Z output state.
Power-off status
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
TCR0n and TCR0m hold count value and stops.
The TO0m output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0m bit is cleared to 0 and the TO0m pin is set
to port mode.)
Hardware Status