UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 268

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
266
Address: FFF9EH
(3) Real-time counter control register 1 (RTCC1)
RTCC1
Symbol
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of
the counter.
RTCC1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of RTCC1, the
ALARMWM register, the ALARMWH register, and the ALARMWW register), set match operation to be invalid (“0”)
for the WALE bit.
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
WALIE
WAFG
WALE
WALE
<7>
0
1
0
1
0
1
Figure 7-4. Format of Real-Time Counter Control Register 1 (RTCC1) (1/2)
After reset: 00H
Match operation is invalid.
Match operation is valid.
Does not generate interrupt on matching of alarm.
Generates interrupt on matching of alarm.
Detection of matching of alarm
Alarm mismatch
WALIE
<6>
R/W
CHAPTER 7 REAL-TIME COUNTER
5
0
User’s Manual U17854EJ9V0UD
Control of alarm interrupt (INTRTC) function operation
WAFG
<4>
Alarm detection status flag
Alarm operation control
RIFG
<3>
2
0
RWST
<1>
RWAIT
<0>

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