UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 339

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(when CSI00:SCK00/P10)
Figure 11-1 shows the block diagram of serial array unit 0.
(when CSI00:SI00/P11/RxD0)
(when UART0:RxD0/P11/SI00)
(when CSI10:SCK10/
(when IIC10:SCL10/
Serial clock I/O pin
Serial data input pin
(when CSI10:SI10/
(when IIC10:SDA10/
(when UART1:RxD1/
Serial data input pin
Serial clock I/O pin
INTTM02
when UART1
when UART0
P04/SCL10)
P04/SCK10)
P03/RxD1/SDA10)
P03/RxD1/SI10)
P03/SI10/SDA10)
f
CLK
Peripheral enable
register 0 (PER0)
SAU0EN
SNFEN00
elimination
Channel 0
enabled/
Channel 1
Channel 2
Channel 3
disabled
SNFEN10
Noise
TXE
elimination
00
enabled/
disabled
Noise
PM10
RXE
00
PRS
013
detection
Edge
Edge/level
DAP
detection
00
PRS
012
CK01
CK01
Edge/level
Edge/level
Edge/level
Serial clock select register 0 (SPS0)
CK01
4
CK01
Serial communication operation setting register 00 (SCR00)
detection
detection
detection
Output latch
Selector
CKP
Figure 11-1. Block Diagram of Serial Array Unit 0
0
PRS
(P10)
00
011
SCK
f
CLK
EOC
0
CK00
00
PRS
/2
CK00
010
CK00
Prescaler
0
CK00
- f
CLK
CKS00
PTC
CHAPTER 11 SERIAL ARRAY UNIT
0
001
/2
PRS
003
Serial mode register 00 (SMR00)
11
MCK
CCS00 STS00 MD002
PTC
Selector
000
0
PRS
002
(Clock division setting block)
User’s Manual U17854EJ9V0UD
4
f
CLK
DIR
1
PRS
00
001
/2
0
- f
CKO02
Serial data register 00 (SDR00)
CLK
SLC
001
PRS
000
/2
11
MD001
SLC
1
000
Serial output register 0 (SO0)
TCLK
CKO00
DLS
002
(Buffer register block)
DLS
001
0
Shift register
Communication controller
Communication controller
Communication controller
Communication controller
(for transmission)
CSI00 or UART0
(for transmission)
DLS
Mode selection
Mode selection
000
0
CSI10 orIIC10
Mode selection
Mode selection
(for reception)
(for reception)
or UART1
UART1
UART0
0
TSF
00
Serial status register 00 (SSR00)
0
BFF
00
SE03 SE02 SE01
SS03 SS02 SS01
ST03
1
0
0
Output latch
Serial flag clear trigger
register 00 (SIR00)
FECT
FEF
00
00
SOE02
SOL02
SO02
(P12)
ST02 ST01
Error controller
Error controller
Error controller
PECT
controller
controller
PEF
Interrupt
00
Output
00
1
0
0
OVCT
OVF
00
00
SOE00
SOL00
SO00
SE00
SS00
ST00
information
Clear
PM12
Error
Serial channel enable
status register 0 (SE0)
Serial channel stop
register 0 (ST0)
Serial output level
register 0 (SOL0)
Serial channel start
register 0 (SS0)
Serial output enable
register 0 (SOE0)
register 0 (NFEN0)
Noise filter enable
SNFEN
Serial data output pin
(when CSI10:SO10/
(when IIC10:SDA10/
(when UART1:TxD1/
Serial data output pin
(when CSI00:SO00/P12/TxD0)
(when UART0:TxD0/P12/SO00)
Serial transfer end interrupt
(when CSI10:INTCSI10)
(when IIC10:INTIIC10)
(when UART1:INTST1)
Serial transfer end interrupt
(when CSI00:INTCSI00)
(when UART0:INTST0)
Serial transfer error interrupt
10
Serial transfer end interrupt
(when UART1:INTSR1)
Serial transfer error interrupt
(INTSRE0)
(INTSRE1)
Serial transfer end interrupt
(when UART0:INTSR0)
SNFEN
00
P02/TxD1)
P03/SI10/RxD1)
P02/SO10)
337