UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 357

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Address: F0124H, F0125H
Address: F0164H, F0165H
(10) Serial channel stop register m (STm)
Symbol
Symbol
ST0
ST1
The lower 8 bits of STm can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Caution Be sure to clear bits 15 to 4 of ST0, and bits 15 to 4, 1 and 0 of ST1 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
STm is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0. Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
STm can set written by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
STm
15
15
n
0
1
0
0
2. When the STm register is read, 0000H is always read.
No trigger operation
Clears SEmn to 0 and stops the communication operation.
(Stops with the values of the control register and shift register, and the statuses of the serial clock I/O pin,
serial data output pin, and the FEF, PEF, and OVF error flags retained
14
14
0
0
Figure 11-13. Format of Serial Channel Stop Register m (STm)
After reset: 0000H
After reset: 0000H
13
13
0
0
12
12
0
0
CHAPTER 11 SERIAL ARRAY UNIT
11
11
0
0
User’s Manual U17854EJ9V0UD
R/W
R/W
10
10
0
0
Operation stop trigger of channel n
9
0
9
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
Note
.)
4
0
4
0
ST0
ST1
3
3
3
3
ST0
ST1
2
2
2
2
ST0
1
1
1
0
ST0
355
0
0
0
0

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