UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 366

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
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RENESAS
Quantity:
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Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.4.2 Stopping the operation by channels
364
The stopping of the operation by channels is set using each of the following registers.
SE0
SE1
ST0
ST1
(a) Serial Channel Enable Status Register m (SEm) … This register indicates whether data
(b) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
Remark
transmission/reception operation of each channel is enabled or stopped.
stopping communication/count by each channel.
*
*
*
*
The SE0 register is a read-only status register, whose operation is stopped by using the ST0 register.
With a channel whose operation is stopped, the value of CKO0n of the SO0 register can be set by software.
The SE1 register is a read-only status register, whose operation is stopped by using the ST1 register.
Because ST0n is a trigger bit, it is cleared immediately when SE0n = 0.
Because ST1n is a trigger bit, it is cleared immediately when SE1n = 0.
15
15
15
15
Figure 11-23. Each Register Setting When Stopping the Operation by Channels (1/2)
0
0
0
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
14
14
14
14
0
0
0
0
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
13
13
13
13
0
0
0
0
1: Clears SE0n to 0 and stops the communication operation
1: Clears SE1n to 0 and stops the communication operation
12
12
12
12
0
0
0
0
11
11
11
11
0
0
0
0
CHAPTER 11 SERIAL ARRAY UNIT
10
10
10
10
0
0
0
0
User’s Manual U17854EJ9V0UD
0
0
0
0
9
9
9
9
8
0
8
0
8
0
8
0
7
0
7
0
7
0
7
0
0: Operation stops
0: Operation stops
0
0
0
0
6
6
6
6
0
0
0
0
5
5
5
5
4
0
4
0
4
0
4
0
SE03
SE13
ST03
ST13
0/1
0/1
0/1
0/1
3
3
3
3
SE02
SE12
ST02
ST12
0/1
0/1
0/1
0/1
2
2
2
2
SE01
ST01
0/1
0/1
0
0
1
1
1
1
SE00
ST00
0/1
0/1
0
0
0
0
0
0

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