UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 448

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

446
Notes 1. When changing the clock selected for f
Remarks 1.
SMRmn Register
CKSmn
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the f
0
1
(CKC) value), do so after having stopped (STm = 000FH) the operation of the serial array
unit (SAU). When selecting INTTM02 and INTTM03 for the operation clock, also stop the
timer array unit (TAU) (TT0 = 00FFH).
frequency (main system clock, subsystem clock), by operating the interval timer for which
f
the TIS0 register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in
channels 2 and 3 of TAU. When changing f
described in Note 1 above.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
SUB
/4 has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of
X: Don’t care
PRS
m13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
Table 11-3 Operating Clock Selection
CHAPTER 11 SERIAL ARRAY UNIT
PRS
m12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
User’s Manual U17854EJ9V0UD
Other than above
PRS
m11
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
SPSm Register
PRS
m10
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
PRS
m03
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
CLK
CLK
PRS
m02
(by changing the system clock control register
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
, however, SAU and TAU must be stopped as
PRS
m01
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
PRS
m00
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
Operation Clock (MCK)
f
f
f
f
f
f
f
f
f
f
f
f
If m = 0: INTTM02,
if m = 1: INTTM03
f
f
f
f
f
f
f
f
f
f
f
f
If m = 0: INTTM02,
if m = 1: INTTM03
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
f
CLK
= 20 MHz
Note 2
Note 2
Note 1
CLK