UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 501

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
Transfer lines
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
Master
Slave
(master transmits, slave receives, and ACKE0 = 1)
ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
H
Generate according to previously set ACKE0 value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
CHAPTER 12 SERIAL INTERFACE IIC0
D0
8
8
User’s Manual U17854EJ9V0UD
Figure 12-19. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IIC0 data write (cancel wait)
1
D7
1
FFH is written to IIC0 or WREL0 is set to 1
D6
2
2
D5
3
3
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