UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 514

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

512
(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
1
No
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN and IICRSV
Checking bus status
IICC0 ← 0XX111XXB
IICC0 ← 1XX111XXB
Enables reserving
interrupt occurs?
Master operation
communication.
IICCL0 ← XXH
SVA0 ← XXH
IICX0 ← 0XH
IICF0 ← 0XH
IICRSV = 0?
Setting port
Setting port
SPD0 = 1?
SPIE0 = 1
IICE0 = 1
INTIIC0
START
starts?
A
Yes
Yes
Yes
Yes
(Communication start request)
•
•
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 12-25. Master Operation in Multi-Master System (1/3)
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Sets the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 12.3 (7) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Releases the bus for a specific period.
Sets the port from input mode to output mode and enables the output of the I
(see 12.3 (7) Port mode register 6 (PM6)).
Slave operation
B
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
STCEN = 1?
Yes
interrupt occurs?
Slave operation
SPIE0 = 0
INTIIC0
Yes
No
Waits for a communication request.
No
interrupt occurs?
SPD0 = 1?
SPT0 = 1
INTIIC0
Yes
Yes
2
C bus
No
No
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
2
C bus (SCL0 and