UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 52

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

50
Data memory
space
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
2. Use of the area FCF00H to FD6FFH is prohibited when using the self-programming function, since this
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7
Program
memory
space
Setting).
When boot swap is used:
area is used for self-programming library.
F F F 0 0 H
F F E F F H
F F E E 0 H
F F E D F H
F 1 0 0 0 H
F 0 F F F H
4 0 0 0 0 H
3 F F F F H
0 0 0 0 0 H
F F F F F H
F C F 0 0 H
F C E F F H
F 0 8 0 0 H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
Special function register (2nd SFR)
General-purpose register
Special function register (SFR)
Figure 3-5. Memory Map (
32 bytes
Flash memory
RAM
47.75 KB
256 bytes
Reserved
Reserved
256 KB
12 KB
Mirror
2 KB
Note 1, 2
CHAPTER 3 CPU ARCHITECTURE
security IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
User’s Manual U17854EJ9V0UD
μ
PD78F1146, 78F1146A)
3 F F F F H
0 1 0 C 4 H
0 1 0 C 3 H
0 1 0 C 0 H
0 1 0 B F H
0 0 0 C E H
0 0 0 C D H
0 0 0 C 0 H
0 0 0 8 0 H
0 0 0 7 F H
0 1 0 C E H
0 1 0 C D H
0 1 0 8 0 H
0 1 0 7 F H
0 1 0 0 0 H
0 0 F F F H
0 0 0 C 4 H
0 0 0 C 3 H
0 0 0 B F H
0 0 0 0 0 H
On-chip debug security
On-chip debug security
ID setting area
Option byte area
ID setting area
Option byte area
CALLT table area
CALLT table area
Vector table area
Vector table area
Program area
Program area
10 bytes
10 bytes
128 bytes
128 bytes
64 bytes
64 bytes
4 bytes
4 bytes
Note 3
Note 3
Note 3
Note 3
0 1 F F F H
Boot cluster 0
Boot cluster 1
Security
Note 4