UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 564

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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14.5.2 CSI master reception
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A flowchart showing an example of setting for CSI master reception is shown below.
• Master reception (256 bytes) of CSI00
• DMA channel 0 is used to read received data and DMA channel 1 is used to write dummy data.
• DMA start source: INTCSI00
• Interrupt of CSI00 is specified by IFC03 to IFC00 = IFC13 to IFC10 (bits 3 to 0 of the DMCn register) = 0110B.
• Data is transferred (received) from FFF10H of the CSI data register (SIO00) to FF100H to FF1FFH of RAM (256
• Transfers dummy data FF101H to FF1FFH (255 bytes) of RAM to FFF10H of the data register (SIO00) of CSI.
(If the same start source is specified for DMA channels 0 and 1, the data of channel 0 is transferred, and then
that of channel 1.)
bytes). (In successive reception mode, the data that is to be received when the first buffer empty interrupt occurs
is invalid because the data has not been received.)
(Dummy data is written to the first byte by using software (an instruction).)
CHAPTER 14 DMA CONTROLLER
User’s Manual U17854EJ9V0UD